This role pays more than
62%
of similar roles. Most pay
$175,000–$223,700
— the shaded band above.
At the midpoint, this role pays about
$208k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
367 open roles
on FindRole.
Listed pay typically runs
$166,400–$249,600
across 367 roles with salary data.
The PLL Design/ Integration Staff Engineer joins the AECG Fabric team within the Programmable Logic Group to lead the design, integration, and characterization of Phase-Locked Loops for FPGA products across cutting-edge process nodes. This role involves architecting and integrating analog and mixed-signal building blocks like VCOs, charge pumps, dividers, and PFDs into complex SoCs. The engineer will manage various PLL topologies including integer-N, fractional-N, and all-digital designs while addressing advanced node challenges such as self-heating and jitter optimization. Key responsibilities include supervising layouts, performing lab bring-up, and conducting system-level simulations using Vivado tools. Required expertise includes IC design, device physics, and silicon manufacturing. Technical skills involve experience with LDOs, SystemVerilog modeling, and clock synthesis techniques like DLLs and CDRs to solve complex programmable clocking challenges in adaptive computing architectures.
Architect and integrate analog/mixed-signal PLL building blocks into FPGA products across cutting-edge process nodes.
Lead the integration of various PLL topologies to meet power, area, jitter, and frequency specifications.
Resolve advanced node challenges including self-heating, electromigration, and device-level noise optimization for jitter reduction.
Supervise and verify layouts produced by physical design engineers to ensure optimal floor planning and parasitic minimization.
Perform PLL bring-up in the lab and conduct performance characterization using state-of-the-art equipment.
Execute system-level simulations and validation for PLL IP integration within FPGA environments using Vivado or similar tools.
What we're looking for
Must have a solid foundation in IC design and manufacturing including analog/digital IP integration.
Experience with PLLs, LDOs, Phase Interpolators, and high-speed dividers across cutting-edge process nodes is required.
Strong understanding of device physics, reliability, and silicon chip manufacturing processes is essential.
Ability to perform post-silicon validation and characterization using state-of-the-art lab equipment.
Proficiency in system-level simulations and validation for PLL IP integration using Vivado or similar tools.
Preferred experience includes designing fractional-N PLLs, All-Digital PLLs (ADPLL), or sub-sampling PLLs.
Familiarity with digital design, digital verification, and SystemVerilog modeling is preferred.
A Master's degree in electrical/electronics engineering is preferred; otherwise, a Bachelor's degree with several years of relevant experience is acceptable.