Pre-Silicon Validation Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$101,400–$152,200 / yr
Posted
12 days ago
Freshness
Confirmed live today
Closes
Apr 13, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k
This role $127k
$85k $251k
below market most similar roles pay here above market

This role pays less than 97% of similar roles. Most pay $168,500–$227,500 — the blue band above. At the midpoint, this role pays about $127k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Pre-Silicon Validation Engineer

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The Pre-Silicon Validation Engineer joins the ASICS Engineering group to support the development and validation of complex ASIC and FPGA-based designs. This role involves developing, deploying, and maintaining emulation environments for complex SoC designs, including porting RTL designs onto platforms like Cadence Palladium, Siemens Veloce, or FPGA prototyping systems. Key responsibilities include developing testbenches, transactors, and verification infrastructure, as well as performing hardware/software co-validation and root-cause failure analysis. The candidate will utilize SystemVerilog, C/C++, Python, and Linux shell scripting to create automation workflows and analyze waveforms. The work focuses on solving functional and performance issues within SoC architectures, utilizing bus protocols like PCIe and DDR. Additionally, the role leverages AI-driven productivity tools to accelerate verification, debug efficiency, and data analysis across the design lifecycle.

Skills

SystemVerilog C/C++ Python ASIC Emulation FPGA Prototyping Linux Cadence Palladium Siemens Veloce Synopsys ZeBu RTL Verification SoC Verification Hardware/Software Co-Validation Shell Scripting PCIe CXL DDR Ethernet AI/ML

What you'll do

  • Develop, deploy, and maintain ASIC and FPGA emulation environments for complex SoC designs.
  • Port RTL designs onto industry-standard emulation platforms like Cadence Palladium or Siemens Veloce.
  • Develop testbenches, transactors, and verification infrastructure using SystemVerilog and C/C++.
  • Analyze and debug functional, performance, and system-level issues within emulation environments.
  • Create Python scripts and workflows to improve regression execution and debug efficiency.
  • Develop methodologies for waveform analysis, signal tracing, and failure root-cause identification.
  • Apply AI-assisted tools and techniques to accelerate verification and data analysis.

What we're looking for

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 0-2+ years of experience in ASIC verification, FPGA prototyping, or hardware emulation.
  • Expertise in SystemVerilog, C/C++, Linux environment and shell scripting, and Python programming.
  • Experience with ASIC and FPGA emulation platforms, RTL debugging, waveform analysis, and design verification methodologies.
  • Knowledge of SoC architectures, bus protocols, and hardware/software interactions.
  • Experience with Cadence Palladium, Protium, Siemens Veloce, or Synopsys ZeBu platforms (preferred).
  • Familiarity with FPGA implementation flows using Xilinx or Intel FPGAs (preferred).
  • Knowledge of PCIe, CXL, DDR, Ethernet, or other high-speed interfaces (preferred).

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