Senior Director Power Architecture, Datacenter AI

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CAAustin, TXHillsboro, ORSanta Clara, CA
Salary
$249,900–$375,800 / yr
Posted
31 days ago
Freshness
Confirmed live yesterday
Closes
Feb 7, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $243k
This role $313k
$161k most similar roles pay here $399k

This role pays more than 92% of similar roles. Most pay $204,525–$280,500 — the shaded band above. At the midpoint, this role pays about $313k versus about $243k for comparable roles.

Based on 239 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Senior Director Power Architecture, Datacenter AI

Senior Director Power Architecture, Datacenter AI serves as the Pre and Post Silicon Power Lead for the ASICS Engineering team. In this role, you will define and validate power consumption targets from IP and SoC levels up to rack scale for complex Datacenter AI systems. You will develop validation and benchmarking plans, lead collaborative test approaches across multiple teams, and create optimization strategies to ensure high power efficiency. Your daily work involves characterizing datacenter workloads, debugging issues during pre-silicon and production phases, and driving technical innovations in system power validation tools and scripts. The role requires expertise in SoC architecture, memory hierarchies, and system interconnects. You will utilize C/C++ and Python for scripting while applying deep knowledge of power management methodologies to solve critical performance challenges within the datacenter AI infrastructure domain.

What you'll do

  • Characterize Data Center workloads on systems to provide inputs for pre-silicon modeling and projection.
  • Define end-to-end power analysis plans for complex Datacenter AI systems from IP to rack scale.
  • Debug power and performance issues during pre-silicon, bring-up, validation, and production phases.
  • Develop optimization strategies to achieve high power efficiency for datacenter AI products.
  • Track test execution across multiple teams to ensure features are performant and power-optimized on schedule.
  • Coordinate with design, architecture, firmware, and software teams to ensure readiness for first silicon arrival.
  • Drive technical innovation by developing tools, scripts, and methodologies for system power validation.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field and 10+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 9+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
  • Experience in pre and post silicon performance and power analysis of SoCs (preferred).
  • Strong programming and scripting skills in C/C++ and Python (preferred).
  • Familiarity with Data Center workloads including compute, memory, and IO bound workloads (preferred).
  • Proven understanding of AI SoC, memory hierarchy, system interconnects, and platform benchmarking (preferred).
  • Experience with power management methodologies and tuning optimization (preferred).

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