Senior DFM Engineer

What you'll do

• Develop new offerings for devices, pcell, and standard cell libraries with internal teams and customers.
• Lead projects regarding design risk assessment for new product introductions.
• Analyze yield to design correlations to improve manufacturing yields and other key performance indicators.
• Use EDA software to perform netlist extraction, timing analysis, and redundancy checks.
• Consult with the fabrication team to identify and implement possibilities for margin improvements.
• Develop methodologies and automation scripts using bash-shell, Python, or Tcl.
• Write SVRF/Tcl code specifically for design risk assessment tasks.
• Present technical information regarding project status and results to senior leadership.

What we're looking for

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering or a related engineering field.
• Experience with the design verification process is required for candidates with degrees in Physics, Chemistry, or Materials Science.
• Experience with Cadence Virtuoso or other EDA tools such as Calibre, Yield Explorer, StarRC/xRC, ICC2, or TCAD.
• Working knowledge of the design-to-mask workflow including schematic, simulation, layout, physical verification, GDSII, and mask.
• Strong scripting experience in tcl, bash/shell, or python.
• Experience with 300mm 16nm/14nm/10nm (or below) wafer manufacturing technology (preferred).
• Authorization to access information subject to U.S. export control laws.