SEG PMU Engineer

What you'll do

• Develop complex digital IPs that meet specific area, power, and performance targets.
• Create precise design specifications for digital control blocks in collaboration with architects.
• Implement physical design ready blocks using SystemVerilog.
• Track project progress and gauge tapeout readiness with project leads.
• Create verification plans in coordination with the DV team.
• Develop lab validation and qualification plans with the silicon validation team.

What we're looking for

• Bachelor's degree or higher in electrical engineering or computer engineering.
• Familiarity with power estimation tools and techniques.
• Familiarity with digital ASIC development flows and milestones.
• Solid understanding of low power design techniques.
• Experience developing digital IPs for SoCs or mixed signal ICs.
• Proven track record of delivering quality designs on schedule.
• Experience with synthesis and static timing tools.
• Expertise in Clock Domain Crossing design and verification techniques.