RTL Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Melbourne, FL
Posted
15 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $199k
$140k most similar roles pay here $251k

This listing doesn't post a salary. Most similar roles pay $168,500–$229,100.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · RTL Design Engineer

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The RTL Design Engineer joins the mixed-signal silicon design team to work on sophisticated digital and mixed-signal circuits. This role involves specifying, micro-architecting, and coding digital blocks while integrating high-performance mixed-signal and analog IPs into high-speed digital circuits. Day-to-day responsibilities include designing, verifying, and supporting lab bring-up by writing assertions, debugging code, and developing test scripts to analyze data. The candidate will utilize Verilog, SystemVerilog, and scripting languages like Perl, JSON, and Python. Technical expertise is required in front-end tools, low power design methodologies, ECO flows, synthesis, static timing, and DFT. Additionally, the role requires knowledge of digital signal processing fundamentals and the use of GenAI tools to optimize RTL code. The work focuses on solving complex challenges within mixed-signal circuit integration and high-speed digital systems.

Skills

Verilog SystemVerilog RTL Design Mixed-Signal Digital Logic UPF CDC RDC LEQ Synthesis DFT Python Perl JSON GenAI Low Power Design ECO

What you'll do

  • Specify and micro-architect digital blocks within sophisticated mixed-signal circuits.
  • Write RTL code for specified digital blocks using Verilog or SystemVerilog.
  • Integrate high-performance mixed-signal and analog IPs into high-speed digital circuits.
  • Develop meaningful assertions and debug code to support the design verification process.
  • Perform lab bring-up of circuits by writing test scripts and analyzing experimental data.
  • Implement low-power design methodologies to reduce dynamic and static IC power.
  • Utilize GenAI tools to design, validate, and optimize SystemVerilog RTL code.

What we're looking for

  • Bachelor of Science degree.
  • Minimum of 10 years of relevant industry experience.
  • Proven knowledge of RTL design, Verilog, and SystemVerilog (preferred).
  • Deep knowledge of front-end tools including simulators, linters, CDC, RDC, LEQ, and UPF (preferred).
  • Knowledge of low power design methodologies and ECO design flows (preferred).
  • Understanding of mixed signal concepts and analog circuit behavioral modeling (preferred).
  • Knowledge of synthesis, static timing, DFT, and SystemVerilog assertions (preferred).
  • Proficiency in scripting languages like Perl, JSON, or Python (preferred).

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