RTL Design Engineer

The RTL Design Engineer joins the mixed-signal silicon design team to develop, verify, and support the lab bring-up of sophisticated digital and mixed-signal circuits with signal processing capabilities. This role involves micro-architecting digital blocks, implementing DSP algorithms into high-performance RTL, and ensuring formal equivalence between custom designs and abstract representations. The engineer will translate complex concepts like filtering and modulation into efficient hardware implementations while collaborating with analog designers and system architects. Key technical requirements include proficiency in Verilog, SystemVerilog, and scripting languages such as Perl or Python. Candidates should possess expertise in synthesis, static timing analysis, and design-for-test methodologies. Additionally, the role requires experience with advanced verification techniques, low-power design, and utilizing GenAI tools for hardware optimization. The work focuses on integrating high-performance mixed-signal IPs into high-speed digital circuits within a complex semiconductor environment.