RTL Design Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Austin, TXMarkham, Ontario, Canada
Salary: $144,800–$217,200 / yr
Posted: 7 days ago
Freshness: Confirmed live yesterday
Closes: Oct 27, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k

This role $181k

$133k $255k

below market most similar roles pay here above market

This role pays less than 59% of similar roles. Most pay $168,425–$229,100 — the blue band above. At the midpoint, this role pays about $181k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · RTL Design Engineer

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RTL Design Engineer The RTL IP Design Engineer joins the Security IP Design team to support the architecture, design, and verification of embedded microprocessor subsystems and hardware accelerators for System-on-Chip products. You will perform block-level RTL design and subsystem-level integration for complex components including security policy management, cryptography, data compression, high-throughput DMA, and power management. Key responsibilities include developing RTL implementations, analyzing regression failures, and collaborating on functional and design-quality closure for lint, timing, and DFT requirements. You must demonstrate proficiency in Verilog, SystemVerilog, and scripting languages like Python, Tcl, Perl, Ruby, and Make. The role requires expertise in AXI, AHB, and AMBA protocols, as well as experience with ASIC development flows, simulation, synthesis, and power-aware verification within processor and accelerator microarchitectures.

Skills

RTL Design SystemVerilog Verilog Python Tcl Perl Ruby Make AXI AHB AMBA C-DPI Linting Synthesis Timing Analysis DFT FPGA Emulation SoC Integration

What you'll do

Develop and maintain block-level RTL IP and MP subsystem specifications, microarchitectures, and implementations.
Design, implement, and debug RTL solutions using AI-powered methodologies and C-DPI based testing.
Analyze regression failures and debug simulations to achieve functional, lint, timing, and DFT signoff requirements.
Contribute to verification planning by reviewing specifications and defining test plans for testbench architecture.
Resolve subsystem and SoC integration issues in collaboration with emulation and post-silicon validation teams.
Provide technical leadership in IP architecture and RTL design methodologies to resolve critical problems.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Master's degree (preferred).
Proficiency in Verilog and SystemVerilog (preferred).
Proficiency in scripting languages such as Python, Tcl, Perl, Ruby, and Make (preferred).
Solid knowledge of traditional and AI-powered RTL design and verification methodologies, including C-DPI based techniques (preferred).
Strong understanding of industry-standard bus and interface protocols, including AXI, AHB, and AMBA (preferred).
Experience with ASIC development tools and flows, including simulation, debug, linting, synthesis, and timing analysis (preferred).
Domain-specific expertise in security, processor subsystems, or accelerators (preferred).

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