RTL Design Engineer

Apple Inc

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Work type
On-site
Location
Austin, TX
Posted
15 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Similar $199k
$140k most similar roles pay here $251k

This listing doesn't post a salary. Most similar roles pay $168,500–$229,100.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · RTL Design Engineer

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The RTL Design Engineer joins the mixed-signal silicon design team to develop, specify, and micro-architect digital and signal processing blocks within sophisticated mixed-signal circuits. This role involves translating DSP concepts like filtering, transforms, and modulation into high-performance RTL implementations while ensuring formal equivalence between custom designs and abstract representations. Day-to-day responsibilities include writing Verilog and SystemVerilog code, creating assertions for verification, and supporting lab bring-up through test scripts and data analysis. The candidate will utilize tools such as Verilog simulators, linters, and clock-domain crossing checkers while applying skills in synthesis, static timing analysis, and design-for-test. Proficiency in Perl, Python, and advanced GenAI tools is preferred to optimize hardware designs. The work focuses on integrating high-performance mixed-signal IPs into high-speed digital circuits with complex signal processing capabilities.

Skills

Verilog SystemVerilog RTL Design DSP Digital Logic Formal Verification Synthesis Static Timing Analysis DFT Python Perl Hardware-Software Co-design Low-Power Design Lab Bring-up Pipelining

What you'll do

  • Specify and micro-architect digital and signal processing blocks within mixed-signal circuits.
  • Develop and optimize RTL code using Verilog or SystemVerilog for high-performance pipelines.
  • Translate DSP concepts like filtering, transforms, and modulation into efficient hardware implementations.
  • Write comprehensive assertions and unit-level testbenches to perform functional verification.
  • Integrate complex IPs and ensure formal equivalence between custom designs and abstract representations.
  • Support lab bring-up by writing test scripts and analyzing silicon performance data.
  • Validate signal processing performance through experimental design and data analysis.

What we're looking for

  • Bachelor of Science in Electrical Engineering.
  • Experience developing and optimizing RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal processing pipelines.
  • Ability to translate DSP concepts into efficient, high-performance RTL implementations.
  • Proficiency in writing assertions, unit-level testbenches, and participating in functional verification using industry-standard methodologies.
  • Experience with front-end tools including Verilog simulators, linters, and clock-domain crossing checkers (preferred).
  • Knowledge of synthesis, static timing analysis, and design-for-test (DFT) (preferred).
  • Proficiency in scripting languages such as Perl or Python (preferred).
  • Advanced skills in formal verification, low-power design, and GenAI tools for SystemVerilog design (preferred).

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