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RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, CA +3 40 days ago $147,900–$221,900
Actively hiring Confirmed live yesterday Trusted Competitive pay
RISCV Verilog VHDL RTL Design Microarchitecture Logic Design Python Perl Power Management Waveform Debugging Simulators Hardware Engineering ISA Scan-dump Memory Dump
2+ yrs exp
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