CPU RTL Methodology Engineer

Qualcomm

Actively hiring
Santa Clara, CA · Austin, TX Posted 56 days ago $198,700$298,100 / year

At a glance

AI generated

TL;DR

Qualcomm Technologies is hiring a senior RTL design engineer to join its CPU design team, where the role involves developing scalable methodologies and automation solutions for efficient RTL workflows. The ideal candidate will support RTL development and debug processes across multiple teams, maintain version control systems like GIT, and develop Python scripts to enhance verification and regression systems. They will also collaborate with CAD teams to integrate RTL tooling into broader design infrastructure and contribute to continuous integration environments. Essential skills include strong knowledge of Verilog/SystemVerilog, experience with RTL databases and version control, advanced scripting in Python, familiarity with CAD tools and CI/CD pipelines, and excellent problem-solving and communication abilities.

Skills

Python Git Verilog SystemVerilog TCL Perl Bash CI/CD CAD RTL

What you'll do

  • Define and develop methodologies to build scalable CPU designs.
  • Support RTL development and debug workflows for CPU design teams.
  • Maintain and enhance RTL databases using GIT and other version control systems.
  • Develop automation scripts in Python to improve RTL verification processes.
  • Interface with CAD teams to align RTL tooling with broader infrastructure.
  • Contribute to continuous integration systems for RTL environments.
  • Document workflows, tools, and best practices for internal teams.

What we're looking for

  • Strong experience in RTL design using Verilog/SystemVerilog and deep understanding of CPU microarchitecture.
  • Proven ability to triage RTL issues and support efficient design/debug workflows.
  • Advanced scripting skills in Python with familiarity in TCL, Perl, or Bash.
  • Experience with CAD tools and automation frameworks for hardware design environments.
  • Familiarity with CI/CD pipelines and build systems for RTL development.

Market check

Salary context

This $198,700–$298,100 range sits above 89% of similar postings on FindRole.

Peer median band

$152,000$241,200

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$160,000$223,700

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 595 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 540 roles with salary data.

Most-posted roles

View all roles at Qualcomm

More like this

Similar roles

RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, CA 18 days ago $142,200$213,400
Verilog VHDL Perl Python Power management Debugging tools RTL design RISCV CPU architecture High-performance systems Low-power microarchitecture Telemetry architecture Interrupt controller Timer synchronization RAS and safety mechanisms Architecture and performance monitoring Scripting languages Simulation tools Waveform debugging tools

CPU Micro-Architect RTL Engineer

Qualcomm

Austin, TX 24 days ago $154,000$231,000
RISC-V RTL Verilog SystemC VHDL Processor pipelines Out-of-order execution Load/store units Caches Cache coherence Memory hierarchy Multi-processor systems Multi-threaded systems Low-power design Performance optimization Area and timing goals Communication skills Collaboration skills Teamwork skills

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA 24 days ago $167,100$250,700
Verilog VHDL Perl Python RTL Microarchitecture Instruction_fetch_and_decode Branch_prediction Out_of_order_execution Integer_and_floating_point_execution Load_store_execution Prefetching Cache_and_memory_subsystems Logic_design_principles Timing_and_power_implications Low_power_microarchitecture_techniques

Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 24 days ago $127,200$190,800
SystemVerilog RTL Verilog Linting CDC LEC CLP Processor integration Bus interface Cache Digital design Logic design

Processor Micro Architect RTL Design Engineer (Multiple Levels)

Qualcomm

San Diego, CA 24 days ago $180,400$270,600
Verilog System Verilog RTL digital design logic design cache memory coherency bus interface multi-core microprocessor architecture low power design functional verification static timing analysis formal verification PLDRC clock domain crossing

CPU Micro-architect/RTL Designer (Multiple Locations)

Qualcomm

Austin, TX 76 days ago $148,300$250,700
Verilog VHDL Perl Python Waveform debugging tools Simulators Instruction fetch and decode Branch prediction Instruction scheduling Register renaming Out-of-order execution Integer execution Floating point execution Load/store execution Prefetching Cache subsystems Memory subsystems Logic design principles Timing analysis Power analysis Low power techniques High performance techniques