CPU RTL Methodology Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$198,700–$298,100 / yr
Posted
12 days ago
Freshness
Confirmed live yesterday
Closes
Feb 26, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $248k
$135k most similar roles pay here $316k

This role pays more than 89% of similar roles. Most pay $168,500–$223,000 — the shaded band above. At the midpoint, this role pays about $248k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU RTL Methodology Engineer

The CPU RTL Methodology Engineer joins the CPU Engineering team to work at the intersection of RTL design and CAD automation. This role focuses on developing methodologies for scalable CPU designs while supporting RTL development, triage, and debug workflows across various teams. The engineer will maintain RTL databases using GIT, develop Python-based automation scripts to improve verification and regression systems, and coordinate with CAD teams to align tools with broader infrastructure. Key responsibilities include contributing to CI/CD pipelines, building tools for RTL environments, and documenting best practices. Candidates must possess expertise in Verilog, SystemVerilog, and CPU microarchitecture, alongside proficiency in Python, TCL, Perl, or Bash. The role addresses the technical challenge of streamlining complex hardware design processes through automated tooling and robust methodology development within a high-performance processor environment.

What you'll do

  • Develop methodologies to build scalable and efficient CPU designs.
  • Support RTL development and debug workflows across multiple CPU design teams.
  • Maintain and enhance RTL databases and repositories using Git version control.
  • Triage RTL issues and collaborate with design teams to resolve them.
  • Create and maintain automation scripts and tools in Python to improve RTL workflows.
  • Align RTL tooling with broader infrastructure by interfacing with CAD teams.
  • Contribute to continuous integration and build systems for RTL environments.
  • Document technical workflows, tools, and best practices for internal teams.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 6+ years of relevant experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of relevant experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 4+ years of relevant experience.
  • Strong experience in RTL design using Verilog and SystemVerilog.
  • Deep understanding of CPU microarchitecture and ability to triage RTL issues.
  • Advanced scripting skills in Python, with familiarity in TCL, Perl, or Bash.
  • Experience with CAD tools, automation frameworks, and CI/CD pipelines for RTL environments.
  • Proficiency in managing RTL databases and version control systems using GIT.

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