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RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, CA +3 30 days ago $142,200–$213,400
Actively hiring Competitive pay
Verilog VHDL Perl Python Power management Debugging tools RTL design RISCV CPU architecture High-performance systems Low-power microarchitecture Telemetry architecture Interrupt controller Timer synchronization RAS and safety mechanisms Architecture and performance monitoring Scripting languages Simulation tools Waveform debugging tools
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