Digital Design RTL Engineer

As a Digital Design RTL Engineer, you will join the engineering team to develop high-quality SystemVerilog RTL for advanced process nodes at 5nm and below. You will operate with a high degree of autonomy, taking designs from initial specification through timing closure and physical design hand-off while collaborating cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and meet project milestones. Your daily work involves performing PPA optimization, clock domain crossing (CDC) analysis, Reset Domain crossing (RDC), and implementing low-power design techniques. The role requires expertise in SystemVerilog and experience with SoC integration, LPDDR5/6, DDR4/5, high-speed SerDes, or HBM protocols. You will solve complex technical challenges related to advanced semiconductor manufacturing and high-speed memory interfaces within the specified hardware architecture requirements.