Principal Physical Design Engineer, STA

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live yesterday
Closes
Apr 28, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $210k
This role $187k
$129k $278k
below market most similar roles pay here above market

This role pays less than 68% of similar roles. Most pay $177,300–$241,750 — the blue band above. At the midpoint, this role pays about $187k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 298 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Principal Physical Design Engineer, STA

Role Posting Log in to save

The Principal Physical Design Engineer, STA joins the Physical Design team within the ASIC Products Division to ensure high-performance, next-generation ASICs meet aggressive performance targets and tight timing requirements. This role involves owning full-chip timing sign-off across PVT corners, authoring SDC for functional and test modes, and managing multi-mode multi-corner scenarios at massive scale. The engineer will deploy AI/ML automation within STA flows to minimize execution runtime, implement ML-based corner reduction, and triage violations across complex clock networks and multi-die boundaries. Key technical requirements include expert proficiency in PrimeTime and Tempus, advanced OCV/SI/IR-drop concepts, and strong scripting skills in Tcl, Python, Perl, and Shell. The work focuses on solving complex timing puzzles at advanced 3nm/2nm nodes and 2.5D/3D chiplet integration.

What does a Physical Design Engineer earn?

Median $183150 from 38 postings across 9 companies.

See salary data

Skills

Static Timing Analysis (STA) PrimeTime Tempus Tcl Python Perl Shell SDC OCV IR-drop Machine Learning AI Physical Design PPA 2.5D/3D Integration HBM3/4 CoWoS

What you'll do

  • Own final timing closure across PVT corners and author SDC for functional and test modes.
  • Deploy AI/ML automation within STA flows to minimize execution runtime and maximize infrastructure efficiency.
  • Implement ML-based corner reduction while ensuring full physical coverage for high-performance ASICs.
  • Triage timing violations and isolate root causes across complex clock networks and multi-die boundaries.
  • Drive timing ECOs using advanced OCV, SI, and IR-drop concepts to optimize PPA.
  • Develop and maintain in-house automation scripts using Tcl, Python, Perl, and Shell.
  • Partner with RTL, Physical Design, and DFT teams to resolve design marginalities.

What we're looking for

  • Bachelor’s degree in Electrical/Computer Engineering.
  • 12+ years of hands-on ASIC STA and timing closure experience.
  • Expert proficiency in sign-off tools such as PrimeTime and Tempus.
  • Advanced expertise in MMMC and OCV management.
  • Strong scripting skills in Tcl, Python, Perl, and Shell.
  • Proven record of utilizing AI plugins and data-mining scripts for runtime reduction and reporting.
  • Exceptional problem-solving and communication abilities.

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