Senior Physical Design Engineer

Broadcom

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Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$121,900–$195,000 / yr
Employment
Full-time
Posted
8 days ago
Freshness
Confirmed live today
Closes
Apr 25, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k
This role $158k
$109k $243k
below market most similar roles pay here above market

This role pays less than 82% of similar roles. Most pay $169,175–$216,250 — the blue band above. At the midpoint, this role pays about $158k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 298 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Senior Physical Design Engineer

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The Senior Physical Design Engineer joins the Physical Design team within the ASIC Products Division to support the development of next-generation Artificial Intelligence and PCIe Switch Products. This role involves leading full-flow implementation from RTL to silicon tape-out, specifically managing block-level and top-level tasks from floorplanning to GDSII stream-out. The engineer will drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced 5nm, 3nm, and 2nm technology nodes. Key responsibilities include multi-corner multi-mode static timing analysis, signal integrity optimization, and power grid optimization. Required technical skills include proficiency with Cadence Innovus, Synopsys PrimeTime, Tempus, RedHawk, and Siemens Calibre. Candidates must also possess expertise in TCL, Python, and Unix shell scripting to automate flows for complex high-frequency networking and AI ASICs.

What does a Physical Design Engineer earn?

Median $183150 from 38 postings across 9 companies.

See salary data

Skills

Cadence Innovus Synopsys PrimeTime Siemens Calibre RedHawk StarRC QRC Python TCL Unix Shell Scripting STA IR-drop EM DRC LVS UPF CPF Floorplanning Placement CTS Routing GDSII Multi-patterning 2.5D/3D Chiplet Integration

What you'll do

  • Lead block-level and top-level implementation from floorplanning to GDSII stream-out.
  • Execute floorplanning, placement, CTS, routing, and timing/power optimization on 5nm, 3nm, and 2nm nodes.
  • Perform multi-corner multi-mode (MCMM) static timing analysis (STA) for signoff.
  • Optimize signal integrity (SI) and power grids for static/dynamic IR-drop and EM.
  • Utilize Cadence Innovus, Synopsys PrimeTime, and RedHawk for physical design flows.
  • Implement high-speed clock networks using H-tree, mesh, and low-power CTS techniques.
  • Manage power-aware implementation flows including UPF/CPF and multi-voltage domains.
  • Develop TCL, Python, and Unix shell scripts to automate design flows and database manipulation.

What we're looking for

  • B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 8+ years of hands-on physical design experience successfully taping out complex high-frequency, ultra-large-scale networking or AI ASICs.
  • Direct experience executing tapeouts in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
  • High proficiency in Cadence Innovus for P&R, Synopsys PrimeTime or Cadence Tempus for STA, and RedHawk or StarRC/QRC for extraction.
  • Advanced TCL, Python, and Unix shell scripting for flow automation and database manipulation.
  • Excellent technical leadership, problem-solving, and cross-functional communication skills.
  • Strong background in high-speed clock network implementation (H-tree, mesh, low-power CTS) (preferred).
  • Experience with power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating) (preferred).

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