Senior Manager, Analog Design

What you'll do

• Manage the design team responsible for defining and implementing circuit architectures for LPDDR IPs.
• Define specifications for high-speed data paths, including calibration and equalization algorithms.
• Develop models for link-level statistical performance simulations to optimize PHY designs.
• Document micro-architecture and algorithms while providing technical guidance to analog, digital, firmware, and verification teams.
• Manage project execution and deliverables across various customers and internal stakeholders.
• Define development flows to improve the efficiency and quality of the design process.
• Oversee the implementation of low-power, area-efficient circuits for LPDDR PHYs.

What we're looking for

• Bachelor's, Master's, or Ph.D. degree in computer engineering or Electrical Engineering.
• Experience managing and contributing to the definition of circuit architecture and design implementation for LPDDR PHYs.
• Ability to develop models for link-level statistical performance simulation of the PHY.
• Proven track record of successfully leading execution of multiple PHY designs with very good Silicon results (preferred).
• Proven successful track record in circuit-architecture and modeling for High Speed IOs (preferred).
• Solid, hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design (preferred).
• Knowledge of industry-standard tools and best practices for PHY modeling using Matlab/Simulink or Verilog/AMS (preferred).
• Minimum 5+ years of team management experience leading multiple IPs from design to production (preferred).