RFIC PLL Design Engineer

What you'll do

• Design and develop analog and digital PLL building blocks including VCO, DCO, MMD, PFD, and filters.
• Develop integrated LOGEN building blocks and top-level designs for wireless SoCs.
• Perform feasibility studies and trade-off analyses to define circuit requirements from concept to transistor-level design.
• Manage layout oversight, floor planning, and verification to ensure successful tape-out.
• Collaborate with RF systems teams to define block-level specifications and manage margin distribution in the chain.
• Address co-existence scenarios and design constraints to meet specific wireless performance requirements.
• Partner with test engineers to debug, optimize, and correlate silicon measurements against design specifications for mass production.

What we're looking for

• Minimum requirement of a bachelor's degree.
• Preferred qualification of a Ph.D. degree.
• Experience in the design and development of analog and digital PLLs and LOGEN for high performance applications.
• Hands-on experience designing building blocks including TDC, Digital Filters, Sigma Delta Modulators, Pre-scalers, MMD, DCO/VCOs, and PFD/CP.
• Understanding of analog, mixed-signal, and RF circuit design concepts like LNAs, PAs, mixers, baseband filters, VGAs, and calibration methods.
• Familiarity with mixed-signal mode verification methodology using SystemVerilog and AMS.
• Experience in PLL and LOGEN silicon characterization and debug.
• Proficiency with tools such as Cadence Virtuoso, Spectre RF, Matlab, and EM simulation (EMX, HFSS).