RFIC PLL Design Engineer

What you'll do

• Design and develop analog and digital PLL building blocks including VCO, DCO, MMD, PFD, and filters.
• Develop analog and digital PLL top levels and LOGEN building blocks for wireless SoCs.
• Perform feasibility studies and trade-off analyses to define circuit requirements from system specifications.
• Execute the full design cycle from initial concept and architecture to transistor-level design and verification.
• Oversee layout, floor planning, and verification of designs to ensure successful tape-out.
• Collaborate with test engineers to debug, optimize, and correlate silicon measurements against specifications.
• Address co-existence scenarios and noise/spur cancellation techniques to meet wireless performance requirements.

What we're looking for

• Minimum requirement of a bachelor's degree.
• Experience in design and development of Analog and Digital PLLs and LOGEN for high performance applications.
• Hands-on experience designing building blocks including TDC, Digital Filters, Sigma Delta Modulators, Pre-scalers, MMD, DCO/VCOs, and PFD/CP.
• Understanding of analog, mixed-signal, and RF circuit design concepts such as LNAs, PAs, mixers, baseband filters, VGAs, and calibration methods.
• Familiarity with mixed-signal mode verification methodology using SystemVerilog and AMS.
• Experience in PLL and LOGEN silicon characterization and debug.
• Preferred Ph.D. degree.
• Proficiency with tools including Cadence Virtuoso, Spectre RF, Matlab, and EM simulation (EMX, HFSS).