Design Engineer

What you'll do

• Contribute to the physical design implementation of large-scale ASICs with multi-hundred-million gate complexity.
• Support floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification activities.
• Utilize commercial and in-house EDA tools for design, implementation, and verification processes.
• Assist in timing analysis, power planning, IR/EM checks, and post-route optimization tasks.
• Collaborate on block-level integration, timing analysis, and design signoff with cross-functional teams.

What we're looking for

• Extensive experience with physical design implementation of large-scale ASICs (multi-hundred-million gate complexity).
• Proficiency in using commercial EDA tools such as Cadence Innovus and Synopsys ICC2 for design and verification.
• Strong background in VLSI design, CMOS logic, digital circuit fundamentals, and ASIC physical design concepts.
• Solid analytical skills with the ability to quickly learn new tools and flows for timing analysis and power planning.
• Bachelor’s or Master’s degree in Electrical or Electronics Engineering required.
• Excellent communication and collaboration skills for working effectively in cross-functional teams.