Physical Design Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Jose, CAAllentownFort Collins, COBroomfield, CO
Salary: $143,800–$230,000 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live yesterday
Closes: Apr 27, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $195k

This role $187k

$133k $242k

below market most similar roles pay here above market

This role pays less than 51% of similar roles. Most pay $163,600–$227,350 — the blue band above. At the midpoint, this role pays about $187k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 298 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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The Physical Design Engineer will join the team to execute critical design implementation activities for ASIC and SoC designs. The role focuses on floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification including LVS and DRC. Key responsibilities involve driving tools and methodologies to achieve specific PPA metrics, performing timing analysis, completing equivalence checks, and implementing timing and functional ECOs. The candidate must possess expertise in place and route, constraints development, and power optimization to ensure right-first time silicon. Required technical skills include proficiency with tools such as Primetime, ICC2, Innovus, Caliber, and LEC. The position requires experience with 7nm and lower technologies to solve complex timing closure and design implementation problems within a global team environment.

What does a Physical Design Engineer earn?

Median $183150 from 38 postings across 9 companies.

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Skills

SoC Design Place and Route STA Timing Closure Clock Tree Synthesis Floor-planning Physical Verification LVS DRC ECO Formal Verification Primetime ICC2 Innovus Caliber LEC

What you'll do

Execute design implementation activities including floor-planning, partitioning, placement, and clock tree synthesis.
Perform timing analysis and achieve timing closure for block and SoC levels.
Conduct physical verification processes including LVS and DRC.
Drive tools and methodologies to achieve specific PPA metrics.
Complete equivalence checks, STA, and power optimization tasks.
Implement timing and functional ECOs.
Apply design methodologies and milestone flows to achieve right-first time silicon.

What we're looking for

BS in Electrical Engineering/Computer Engineering or related field and 12+ years of related experience.
MS in Electrical Engineering/Computer Engineering or related field and 10+ years of related experience.
Hands-on experience with timing analysis and place and route tools for ASIC/SoC Design is a must.
Proficient in design implementation activities at both block and SoC levels.
Well experienced in floor-planning, partitioning, placement, clock tree synthesis, route, and physical verification.
Experience with formal verification, timing analysis, and ECO implementation.
Experience with tools such as Primetime, ICC2, Innovus, Caliber, and LEC is highly desirable (preferred).
Full chip tapeout experience based on 7nm and lower technologies is highly preferred (preferred).

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