VLSI CAD Timing Intern, Applied AI

What you'll do

• Support static timing analysis (STA) flows using industry tools like PrimeTime and Tempus for advanced ASIC designs.
• Develop and automate timing, constraints, and QoR validation flows using scripting and data-driven methods.
• Analyze timing reports, constraints, and design data across various corners and modes to improve closure predictability.
• Contribute to AI-assisted approaches for timing analysis, constraint checking, and flow optimization.
• Explore the influence of physical effects like IR drop, crosstalk, aging, and thermal impact on timing.
• Lead end-to-end solution development for data generation, model training, and agentic automation in timing workflows.

What we're looking for

• Currently pursuing a Master’s or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Possess academic knowledge in VLSI/ASIC design, digital circuits, or computer architecture.
• Have exposure to applying agentic AI to back-end VLSI tasks such as floorplanning, timing closure, or physical verification.
• Familiarity with the basics of static timing analysis, constraints, or digital design flows.
• Knowledge in scripting or programming (Python preferred).
• Comfort working with data, reports, and technical problem-solving in complex systems.
• Academic projects, research, or internships related to VLSI, physical design, STA, or EDA tools (preferred).
• Exposure to TCL, machine learning, data analysis, or AI concepts applied to engineering problems (preferred).