Panel Packaging Technology Enablement Director

Applied Materials

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Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$176,000–$242,000 / yr
Employment
Full-time
Posted
11 days ago
Freshness
Confirmed live today

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $235k
This role $209k
$163k $302k
below market most similar roles pay here above market

This role pays less than 73% of similar roles. Most pay $208,300–$262,462 — the blue band above. At the midpoint, this role pays about $209k versus about $235k for comparable roles.

Based on 240 similar postings.

Employer

About Applied Materials

Applied Materials is the world''s largest supplier of equipment, services, and software for the semiconductor and display industries, enabling the production of chips and advanced displays. Industry: Semiconductor Equipment

Applied Materials currently has 337 open roles on FindRole.

Listed pay typically runs $124,000–$171,000 across 219 roles with salary data.

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At a glance

TL;DR · Panel Packaging Technology Enablement Director

The Panel Packaging Technology Enablement Director leads a multidisciplinary team of process, integration, and applications engineers to develop and validate panel process solutions. This role involves defining the technology enablement roadmap, translating AI package architecture requirements into unit process targets, and managing complex integration programs from concept through customer transfer. Key responsibilities include planning integrated process flows for core formation, through-glass via fabrication, metallization, and fine-line RDL. The position requires expertise in 2.5D/3D packaging, PVD, plating, etch, lithography, and dielectric processes. The Director serves as a technical lead for substrate manufacturers, OSATs, and foundries, addressing high-value problems in panel-level packaging for AI accelerators and high-performance computing. Success requires managing joint development programs, establishing industry standards, and driving cross-functional coordination to deliver integrated packaging solutions.

What you'll do

  • Define and execute the panel technology enablement roadmap to meet AI package architecture requirements.
  • Plan integrated process flows for core formation, through-glass via fabrication, metallization, and interconnects.
  • Lead complex integration programs from initial concept through customer transfer and customized process development.
  • Serve as the primary technical lead for strategic customers, including substrate manufacturers, OSATs, and foundries.
  • Establish and oversee joint development programs, evaluations, and beta-site activities at customer manufacturing sites.
  • Build and manage strategic partnerships with materials suppliers, research institutes, and equipment partners to close ecosystem gaps.
  • Build and lead a multidisciplinary team of process, integration, and applications engineers.
  • Manage resource and budget planning while aligning team output with business unit revenue and market share objectives.

What we're looking for

  • Ph.D. in chemistry, materials science, chemical engineering, electrical engineering, physics, or a related field.
  • M.S. in a related field with 15+ years of experience.
  • 12+ years of experience in semiconductor packaging, substrate, or interconnect technology development.
  • Hands-on technical depth in advanced packaging integration, such as 2.5D/3D packaging, high-density substrates, fan-out, or build-up processing.
  • Working knowledge of PVD, plating, etch, lithography, and dielectric processes.
  • Demonstrated record of leading engineering teams and delivering complex technology programs to customers or into high-volume manufacturing.
  • Experience presenting to and negotiating with senior customer and partner leadership.
  • Track record of patents, publications, and conference presentations.
  • Direct experience with panel-format processing, glass core substrates, through-glass vias, or fine-line RDL at sub-5 µm line/space (preferred).
  • Familiarity with AI accelerator and HPC package architectures, including chiplet integration and HBM co-packaging (preferred).
  • Established relationships across the Asia-Pacific substrate and OSAT ecosystem and participation in industry consortia (preferred).
  • Experience managing joint development agreements and multi-party technical programs (preferred).

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