New Graduate Engineer, ASIC Design (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Hawthorne, CA
Salary: $125,000–$150,000 / yr
Posted: 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $174k

This role $138k

$114k most similar roles pay here $230k

This role pays less than 77% of similar roles. Most pay $140,000–$208,875 — the shaded band above. At the midpoint, this role pays about $138k versus about $174k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 614 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 446 roles with salary data.

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At a glance

TL;DR · New Graduate Engineer, ASIC Design (Starshield)

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Join the Starshield team as a New Graduate Engineer in ASIC Design, where you will work closely with experienced engineers to develop advanced semiconductor technologies. Your responsibilities include designing and implementing RTL code for complex systems, utilizing tools like Cadence or Synopsys, and collaborating on projects that involve AXI, AHB protocols, and other critical interfaces. Ideal candidates are graduating in 2026 or 2027 with a strong background in FPGA/ASIC development and a degree in Electrical Engineering, Computer Science, or related fields. Familiarity with Verilog or SystemVerilog is essential, along with knowledge of scripting languages such as Python for automation tasks. This role involves tackling intricate challenges in national security technology, requiring a deep understanding of digital design principles and the ability to work within strict ITAR compliance guidelines.

Skills

RTL FPGA ASIC AXI AHB CI/CD

What you'll do

Design and implement RTL code for ASICs using industry-standard design flows.
Develop testbenches to verify the functionality of digital circuits at the register transfer level.
Collaborate on the integration of IP cores into complex SoC designs.
Optimize circuit performance by analyzing simulation results and making iterative improvements.
Participate in the validation of FPGA prototypes before ASIC tapeout.

What we're looking for

Graduating with a bachelor’s, master’s degree, or PhD in 2026 or 2027.
At least 1 year of experience in RTL implementation and/or FPGA/ASIC development.
Strong knowledge of AXI, AHB, and other bus protocols.
Ability to meet U.S. Department of State ITAR requirements.
Excellent problem-solving skills for complex engineering challenges.
Proficient in relevant software tools and programming languages used in ASIC design.

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