IC Verification Engineer

Broadcom

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Employment
Full-time
Posted
36 days ago
Freshness
Confirmed live today
Closes
Mar 20, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $187k
$133k $240k
below market most similar roles pay here above market

This role pays less than 51% of similar roles. Most pay $168,500–$223,000 — the blue band above. At the midpoint, this role pays about $187k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · IC Verification Engineer

The IC Verification Engineer will join the team to architect and develop scalable, reusable testbench environments using established verification methodologies. The primary responsibilities include driving test plans for block, core, and SOC features, writing functional coverage, and building pseudo-random tests to achieve full coverage and verification closure. The role involves debugging regression failures, analyzing coverage gaps, mentoring junior team members, and leading the documentation of verification strategies. Key technical requirements include proficiency in SystemVerilog and UVM or VMM methodologies. Candidates must possess experience with complex protocols like PCI Express or AXI. The work involves managing the full ASIC cycle from architecture development to tapeout, focusing on verification quality and efficiency improvements for complex designs and multi-layered protocols.

What you'll do

  • Architect and develop scalable and reusable testbench environments using standard verification methodologies.
  • Drive test plans for all features across Block, Core, and SOC levels.
  • Write functional coverage for features and build pseudo-random tests to achieve full coverage.
  • Debug regression failures and analyze functional coverage gaps to improve test coverage.
  • Lead the documentation of verification strategies, including test plans and verification environments.
  • Lead design and architecture reviews to ensure verification quality and efficiency.
  • Mentor junior team members and provide technical guidance.

What we're looking for

  • Bachelor’s degree in Electrical/Electronics/Equivalent with 12+ years of relevant experience.
  • Master’s degree in Electrical/Electronics/Equivalent with 10+ years of relevant experience.
  • 10+ years of experience in developing complex Verification Environments, developing Test plans, Functional coverage, and pseudo-random testing.
  • Experience completing a full ASIC cycle from Architecture development to Tapeout with a focus on Verification leading a Core.
  • Very proficient in System Verilog and Verification Methodologies like UVM/VMM.
  • Good debug skills in analyzing regression failures and understanding of complex designs.
  • Good understanding of a complex protocol like PCI Express or other multi-layered protocols.
  • Experience with PCIe protocol, Makefiles, and AXI Compensation (preferred).

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