Lead ASIC Verification Engineer

General Dynamics

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Boise, IDSalt Lake City, UTScottsdale, AZSan Jose, CA
Salary
$173,032–$190,000 / yr
Posted
1 day ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $182k
$138k $240k
below market most similar roles pay here above market

This role pays less than 55% of similar roles. Most pay $168,500–$224,075 — the blue band above. At the midpoint, this role pays about $182k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About General Dynamics

General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.

General Dynamics currently has 1351 open roles on FindRole.

Listed pay typically runs $124,093–$150,385 across 1176 roles with salary data.

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At a glance

TL;DR · Lead ASIC Verification Engineer

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The Lead ASIC Verification Engineer joins a cross-functional team at Idaho Scientific to support the Bitttercloud II program. This role involves designing and architecting advanced embedded security technologies to protect U.S. defense systems from cyber exploitation, physical attacks, and supply chain compromise. The engineer leads ASIC verification at the block, subsystem, and full-chip levels, developing verification plans, schedules, and coverage goals. Daily tasks include building reusable SystemVerilog and UVM test environments, executing simulations, formal verification, and emulation activities, and performing root-cause analysis on failures. Required skills include proficiency in SystemVerilog, UVM, assertions, and scripting languages like Perl, Tcl, Bash, and Python. The role utilizes tools such as VCS, Verdi, and Questa to verify secure processors, anti-tamper architectures, and cryptographic IP for government cybersecurity requirements.

Skills

ASIC Verification SystemVerilog UVM RTL Digital Logic Python Perl Tcl Bash VCS Verdi Questa Formal Verification CDC RDC Emulation Linux Version Control Agile

What you'll do

  • Lead ASIC verification at the block, subsystem, and full-chip levels.
  • Develop verification plans, schedules, coverage goals, and completion criteria.
  • Build reusable SystemVerilog/UVM test environments and verification components.
  • Plan and execute simulation, regression, formal verification, and emulation activities.
  • Lead failure investigation, root-cause analysis, and corrective-action verification.
  • Verify third-party and custom IP for functional and integration compliance.
  • Provide technical direction and mentoring to verification engineers.
  • Improve verification processes, automation, metrics, and reusable assets.

What we're looking for

  • U.S. citizenship is required.
  • Department of Defense Secret security clearance is required at time of hire.
  • Bachelor's degree in Electrical or Computer Engineering, or a related field, plus 10 years of relevant experience.
  • Master's degree plus a minimum of 8 years of relevant experience.
  • Strong proficiency in SystemVerilog, UVM, assertions, coverage, and regression testing.
  • Experience with scripting languages such as Perl, Tcl, Bash, and Python.
  • Experience with ASIC simulation and debug tools such as VCS, Verdi, Questa, or equivalent tools.
  • Experience with formal verification, CDC/RDC analysis, or low-power verification (preferred).

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