Junior Design Verification Engineer

Amazon Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Austin, TXSunnyvale, CA
Salary: $114,600–$160,400 / yr
Posted: 12 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $175k

This role $138k

$104k $212k

below market most similar roles pay here above market

This role pays less than 96% of similar roles. Most pay $161,500–$187,850 — the blue band above. At the midpoint, this role pays about $138k versus about $175k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · Junior Design Verification Engineer

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Junior Design Verification Engineer, Amazon Leo joins the sub-team responsible for defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This role involves implementing a state of the art verification environment to test RTL against reference Matlab/C models. Key responsibilities include developing detailed test plans, writing tests, running regressions, collecting coverage matrices, and participating in the validation of ASIC implementations. The engineer will work with design and communication systems teams to perform system level verification using test benches constructed using UVM. Required skills include Verilog, SystemVerilog, and UVM, with preferred experience in Matlab, System C, C, modem design verification, and formal verification techniques. The work focuses on defining modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

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Skills

SystemVerilog UVM Verilog Matlab C System C RTL ASIC Formal Verification DSP CMOS Coverage Analysis

What you'll do

Implement a state-of-the-art verification environment to test RTL against reference Matlab/C models.
Develop detailed test plans and write tests to execute regressions and collect coverage matrices.
Validate ASIC implementations using Verilog and SystemVerilog.
Perform system-level verification using test benches constructed with UVM.
Develop a highly automated environment to run regressions and maintain the database organization.
Report verification progress and coverage metrics to the program.

What we're looking for

Bachelor's degree in Electrical or Communications Engineering or a related field.
2+ years in verification, preferably in communication systems.
2+ years in UVM.
U.S. citizen, national, permanent resident, refugee, or asylee.
Master's or Ph.D. degree in Electrical / Communications Engineering (preferred).
3+ years in digital verification, preferably in communication systems (preferred).
Familiarity with Matlab, modem design verification, and System C, C, or Matlab model development or DV integration (preferred).
Export control laws and regulations, candidates.

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