Junior Design Verification Engineer

Amazon Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $114,600–$160,400 / yr
Posted: 14 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $180k

This role $138k

$104k most similar roles pay here $214k

This role pays less than 93% of similar roles. Most pay $161,500–$197,750 — the shaded band above. At the midpoint, this role pays about $138k versus about $180k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 535 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 533 roles with salary data.

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At a glance

TL;DR · Junior Design Verification Engineer

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Junior Design Verification Engineer, Amazon Leo joins the sub-team responsible for defining and implementing digital chip SOCs for communication via Low Earth Orbit satellites and gateways. This role focuses on developing a groundbreaking wireless solution involving modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. You will implement state of the art verification environments to test RTL against reference Matlab or C models, develop detailed test plans, run regressions, and collect coverage matrices. The position involves validating ASIC implementations in Verilog and SystemVerilog while participating in system level verification using UVM test benches. Key technical requirements include experience with UVM, communication systems, and potentially Matlab, System C, formal verification techniques, and AI-assisted tools to accelerate workflows like testbench generation and debug for the wireless communications product area.

What does a Design Verification Engineer earn?

Median $187850 from 51 postings across 8 companies.

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Skills

UVM SystemVerilog Verilog Matlab C System C RTL Formal Verification ASIC DSP Coverage Analysis Testbench CMOS Digital Verification

What you'll do

Implement a state-of-the-art verification environment to test RTL against reference Matlab and C models.
Develop detailed test plans and write tests for the verification process.
Run regressions and collect coverage matrices to report progress to the program.
Validate ASIC implementations using Verilog and SystemVerilog.
Perform system-level verification using test benches constructed with UVM.
Develop a highly automated environment to run regressions and maintain database organization.

What we're looking for

Bachelor's degree in Electrical Engineering, Communications Engineering, Computer Science, or a related field (or equivalent experience).
2+ years of experience in verification, preferably in communication systems.
2+ years of experience in UVM.
Master's or Ph.D. degree in Electrical or Communications Engineering (preferred).
3+ years of experience in digital verification, preferably in communication systems (preferred).
Experience with Matlab, modem design verification, and System C/C development or integration (preferred).
Familiarity with formal verification techniques and AI-assisted tools for verification workflows (preferred).
Must be a U.S. citizen, national, permanent resident, or lawfully admitted as a refugee or granted asylum due to export control laws.

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