Intern, RTL Power Macromodeling Engineer

Samsung Semiconductor

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Work type
Hybrid
Location
San Jose, CA
Employment
Intern
Posted
3 days ago
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Confirmed live today
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About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

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TL;DR · Intern, RTL Power Macromodeling Engineer

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JOB TITLE: Intern, RTL Power Macromodeling Engineer The Power & Thermal Lab is seeking an intern to support research and product teams in developing and validating IP-level power macromodels for AI memory components. You will work on real-world projects to create models for components like PHY, memory controllers, interconnects, and TSVs. Your daily tasks include extracting activity, value, and state-dependent power features from RTL, SystemC, and C simulations. You will use analytical models, lookup tables, FSMs, and neural networks to build these models, validating them against gate-level power analysis and silicon data. Required skills include Verilog, SystemVerilog, SystemC, C++, and Python. You will address the technical challenge of power and heat bottlenecks in AI memory systems by delivering validated models into a trace-driven power and thermal simulator flow.

Skills

RTL SystemC Verilog SystemVerilog C++ Python Power Analysis PrimeTime PX StarRC VCS PowerArtist McPAT CACTI Wattch SPICE CMOS S-parameters UCIe Regression Checks

What you'll do

  • Develop IP-level power macromodels for AI memory components using analytical models, lookup tables, and neural networks.
  • Extract activity, value, and state-dependent power features from RTL, SystemC, and C simulations.
  • Support model calibration using synthesis-assisted anchors, circuit-level references, and measured data.
  • Validate models against RTL and gate-level power analysis and silicon data to improve accuracy.
  • Deliver validated models and regression checks into the trace-driven flow.
  • Work with software engineers to define and implement model interfaces.

What we're looking for

  • MS or PhD in Electrical and Computer Engineering, Computer Science, or a related field.
  • Must have at least 1 academic quarter/semester remaining.
  • Experience in RTL design and analysis using Verilog, SystemVerilog, and SystemC.
  • Proficiency in solid C++ or Python.
  • Understanding of dynamic and leakage power in CMOS and interconnects.
  • Ability to abstract circuit behavior into compact models.
  • Experience with power analysis tools such as PrimeTime PX, StarRC, VCS, or PowerArtist (preferred).
  • Experience with architecture level modeling tools such as McPAT, CACTI, or Wattch, S-parameters and SPICE, UCIe or high speed I/O or 2.5D packaging (preferred).

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