Interconnect Micro-architect/RTL Design Engineer

Amd

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$178,400–$267,600 / yr
Posted
87 days ago
Freshness
Confirmed live today
Closes
Jul 8, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $223k
$136k most similar roles pay here $282k

This role pays more than 70% of similar roles. Most pay $168,500–$234,825 — the shaded band above. At the midpoint, this role pays about $223k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 512 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 512 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Interconnect Micro-architect/RTL Design Engineer

Role Posting Log in to save

As an Interconnect Micro-architect/RTL Design Engineer on the Infinity Fabric Architecture and RTL team, you will design and implement key components of a scalable, coherent on-chip network to enable high-speed communication across CPUs, GPUs, and accelerators. You will define microarchitecture for interconnect subsystems and develop synthesizable RTL using Verilog or SystemVerilog while optimizing designs for power, performance, area, and timing goals. Your daily work involves collaborating with cross-functional teams to deliver hardware for servers, AI platforms, client devices, and gaming systems. The role requires expertise in network-on-chip, cache/memory subsystems, and processor architecture including coherency. You will also develop assertions, contribute to coverage strategies, and debug issues during pre-silicon and post-silicon phases. Required skills include knowledge of digital design fundamentals, high-speed hardware systems, and familiarity with Python, C, or C++.

Skills

Verilog SystemVerilog RTL Design Network-on-Chip NoC Microarchitecture x86 ARM Python C C++ Digital Design DFT

What you'll do

  • Define microarchitecture for interconnect and network-on-chip components.
  • Develop and implement synthesizable RTL using Verilog or SystemVerilog.
  • Optimize hardware designs to meet power, performance, area, and timing goals.
  • Design scalable, coherent interconnect solutions across multiple product lines.
  • Support unit-level validation and provide high-quality RTL to verification teams.
  • Develop assertions and contribute to coverage strategies for design verification.
  • Debug design issues during both pre-silicon and post-silicon phases.
  • Create clear and maintainable technical documentation for designs.

What we're looking for

  • Develop and implement synthesizable RTL using Verilog/SystemVerilog.
  • Define microarchitecture for interconnect, fabric, or network-on-chip (NoC) components.
  • Optimize designs to meet power, performance, area, and timing goals.
  • Support unit-level validation, develop assertions, and contribute to coverage strategies.
  • Debug design issues during pre-silicon and post-silicon phases.
  • Experience with interconnect, NoC, or cache/memory subsystem design (preferred).
  • Understanding of processor architecture, including coherency and memory systems (preferred).
  • BS, MS, or PhD degree in Electrical or Computer Engineering (preferred).

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