GPU PD Engineer (Austin/San Diego)

Qualcomm

Quick summary

Work type
On-site
Location
Austin, TXSan Diego
Salary
$195,200–$292,800 / yr
Posted
127 days ago
Closes
Aug 8, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $244k
$135k most similar roles pay here $310k

This role pays more than 86% of similar roles. Most pay $165,812–$235,750 — the shaded band above. At the midpoint, this role pays about $244k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 745 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 423 roles with salary data.

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At a glance

TL;DR · GPU PD Engineer (Austin/San Diego)

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As a senior physical design engineer at Qualcomm Technologies, Inc., you will join the integrated graphics core team to enhance Power, Performance, and Area (PPA) metrics for cutting-edge GPUs. Your daily tasks include implementing complex high-frequency designs from RTL to GDS using Synopsys Fusion Compiler, ICC2, and Cadence Genus/Innovus, collaborating with RTL designers to optimize micro-architecture, and developing automation in design flows. You will need expertise in static timing analysis, PDN network design, scripting languages like Tcl or Python, and sub-micron technology nodes such as 4nm. This role demands a deep understanding of CMOS circuits, innovative problem-solving skills, and the ability to work effectively with multidisciplinary teams to drive successful tape-outs at advanced process nodes.

Skills

Synopsys_Fusion_Compiler ICC2 Cadence_Genus Cadence_Innovus TCL Perl Python Verilog System_Verilog DFT Place_and_Route Timing_Analysis Reliability_Signoff Sub_micron_Technology_Pods 4nm_Process_Node RTL_Design CMOS_Stdcell Memory_Circuits GPU_Micro-Architecture

What you'll do

  • Perform physical implementation of integrated graphics core designs from RTL to GDS.
  • Utilize advanced tools like Synopsys Fusion Compiler and Cadence Genus for design optimization.
  • Enhance Power, Performance, and Area (PPA) metrics in complex high-frequency blocks.
  • Collaborate with RTL designers to improve power and performance bottlenecks.
  • Develop and improve automation in design flows and methodologies for efficiency.
  • Scripting skills in tcl, perl or python to automate tasks and enhance productivity.

What we're looking for

  • Experience in physical design implementation including floor-planning, placement, and routing for complex high-frequency designs.
  • Proficiency with Synopsys Fusion Compiler, ICC2, and Cadence Genus/Innovus for physical synthesis and implementation.
  • Strong understanding of static timing analysis, power analysis, PDN network, and CMOS stdcell design techniques.
  • Ability to innovate solutions for improving power efficiency and eliminating performance bottlenecks in GPU micro-architecture.
  • Hands-on experience with sub-micron technology process nodes (e.g., 4nm) and complex designs pushing PPA limits.
  • Solid scripting skills in Tcl, Perl, or Python for automation and tool development.
  • Proven track record of successful innovation and collaboration across multidisciplinary teams.

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