ASIC/RTL Design Engineer for High-speed Interfaces
Qualcomm
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How this pay compares to similar roles
This role pays more than 84% of similar roles. Most pay $167,375–$216,250 — the shaded band above. At the midpoint, this role pays about $240k versus about $192k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 623 open roles on FindRole.
Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.
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The Senior Lead High-speed Electrical/Optical Post-Silicon Engineer joins the Central Hardware Systems team to drive measurements, validation, and debug for next-generation 224G/448G electrical and optical interconnects. This role involves performing channel characterization across packages, PCBs, and cables while correlating bench data with simulations. The engineer will lead post-silicon bring-up, perform SerDes validation, and conduct PDN failure isolation involving rail noise and power delivery issues. Key responsibilities include developing automation scripts, data reduction tools, and stress content to identify electrical or optical failures. Required expertise includes high-speed digital design, SI/PI fundamentals, and proficiency with VNAs, oscilloscopes, BERTs, and TDR equipment. The role addresses complex technical challenges in link training, equalization, and signal integrity for standards like PCIe, CXL, and Ethernet while ensuring system readiness across various hardware platforms and software environments.
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