Graphics FE Implementation Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $129,300–$194,700 / yr
Posted: 15 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $207k

This role $162k

$113k most similar roles pay here $279k

This role pays less than 88% of similar roles. Most pay $177,300–$236,487 — the shaded band above. At the midpoint, this role pays about $162k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · Graphics FE Implementation Engineer

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As a Graphics FE Implementation Engineer, you will join the GPU FE Implementation team to optimize and deliver world-class GPUs into Apple Silicon. You will be responsible for RTL to netlist generation while collaborating closely with the RTL and Physical design teams. Your daily responsibilities include delivering key netlist quality milestones for your partition, engaging in Lint, CDC, and Logic equivalence checks, and supporting ECO generation activities. The role requires proficiency in at least one scripting language such as Python, Perl, or Tcl. Preferred technical skills include familiarity with Verilog, System Verilog, DFT methodologies, and static timing analysis concepts like setup and hold timing. You will also utilize industry standard rtl2gds tools for synthesis, place and route, and manage CMOS device characteristics to balance area, timing, and power tradeoffs.

Skills

RTL System Verilog Verilog Python Tcl Perl Synthesis Static Timing Analysis DFT CDC ECO CMOS VLSI Digital Logic Design Netlist Generation Place and Route

What you'll do

Perform RTL to netlist generation for GPU components.
Deliver key netlist quality milestones for assigned partitions.
Execute Lint, CDC, and Logic equivalence checks.
Support ECO generation activities during the design process.
Implement hardware designs using Verilog and System Verilog.
Manage synthesis, place and route, and static timing analysis tasks.
Address Clock/Reset domain crossing and Voltage crossing principles.
Utilize scripting languages like Python, Perl, or Tcl for automation.

What we're looking for

Bachelor of Science degree required.
Relevant coursework in Computer Architecture, Digital Logic Design, and CMOS VLSI design.
Experience with at least one scripting language such as Python, Perl, or Tcl.
Familiarity with Verilog and System Verilog (preferred).
Exposure to industry standard rtl2gds tools for synthesis, place and route, and static timing analysis (preferred).
Exposure to Clock/Reset domain crossing or Voltage crossing principles (preferred).
Familiarity with DFT methodologies (preferred).
Knowledge of static timing analysis concepts and CMOS device characteristics for area/timing/power tradeoffs (preferred).

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