EM Design Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $139,400–$209,200 / yr
Posted: 46 days ago
Freshness: Confirmed live yesterday
Closes: Jan 23, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $171k

This role $174k

$120k most similar roles pay here $219k

This role pays more than 59% of similar roles. Most pay $142,575–$199,875 — the shaded band above. At the midpoint, this role pays about $174k versus about $171k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · EM Design Engineer

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The EM Design Engineer joins the RF EM Team to design and develop passive components for highly integrated RF integrated circuits using 6nm and 14ff CMOS and SOI technologies. The role involves collaborating with circuit design teams to optimize component sizes and performance, delivering compact models, and ensuring DRC clean physical designs. Key responsibilities include executing isolation analysis to reduce on-chip and chip-to-package coupling while optimizing multichip carriers for RF systems regarding loss and isolation. Candidates must possess experience in designing inductors, transformers, MOM capacitors, and passive filters. Required technical skills include EM simulation techniques using MoM solvers, HFSS, and EMX, alongside circuit design and layout expertise using Cadence tools and Agilent ADS. The work focuses on solving complex electromagnetic challenges within the domain of advanced wireless product integration.

Skills

RFIC Design EM Simulation Circuit Modeling HFSS EMX Cadence Virtuoso Agilent ADS MoM EM Solvers RLCK Model Extraction ASIC Design Layout 14ff CMOS Passive Components

What you'll do

Design and develop RF passive components for integrated circuits using 6nm and 14ff CMOS and SOI technologies.
Optimize component sizes and performance in coordination with the circuit design team.
Deliver physical designs that are DRC clean and include accurate compact models.
Perform isolation analysis to reduce on-chip and chip-to-package coupling.
Optimize multichip carriers for RF systems by focusing on loss and isolation.
Extract RLCK models for multiport passive components.
Use EM simulation tools to predict circuit-level electric and magnetic coupling.

What we're looking for

Bachelor's degree in Electrical Engineering with 3+ years of experience designing RF/Analog circuits for wireless products.
Master's degree in Electrical Engineering or a related field and 2+ years of ASIC design or verification experience.
PhD in Electrical Engineering or a related field.
At least 2 years of academic or professional experience using two or more tools including CADENCE, Virtuoso, or ADS.
Experience in the design and simulation of RF passive components like inductors, transformers, MOM capacitors, and filters.
Proficiency with EM simulation techniques and tools such as MoM solvers, HFSS, and EMX.
Experience with circuit design and layout using Cadence tools and Agilent ADS.
Ability to perform compact RLCK model extraction of multiport passive components.

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