EM Design Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$147,900–$221,900 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $180k
This role $185k
$122k $233k
below market most similar roles pay here above market

This role pays more than 59% of similar roles. Most pay $149,818–$209,500 — the blue band above. At the midpoint, this role pays about $185k versus about $180k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · EM Design Engineer

The EM Design Engineer joins the RF EM Team to design and develop RF passive components for highly integrated RF integrated circuits. Working within deep sub-micron 6nm and 14ff CMOS and SOI technologies, the engineer will collaborate with the circuit design team to optimize component sizes and performance for RF circuit blocks. Key responsibilities include delivering components with compact models and DRC clean physical designs, executing isolation analysis to reduce on-chip and chip-to-package coupling, and optimizing multichip carriers for RF systems. The role requires proficiency in EM simulation techniques using MoM EM solvers, HFSS, and EMX, alongside experience with Cadence tools, Virtuoso, and Agilent ADS. Candidates must demonstrate expertise in designing inductors, transformers, MOM capacitors, and passive filters while performing compact RLCK model extraction.

What you'll do

  • Design and develop RF passive components for 6nm and 14ff CMOS and SOI technologies.
  • Optimize component sizes and performance for use in RF circuit blocks.
  • Deliver DRC clean physical designs and compact models for components.
  • Execute isolation analysis to reduce on-chip and chip-to-package coupling.
  • Optimize multichip carriers for RF systems focusing on loss and isolation.
  • Perform EM simulations using tools like MoM solvers, HFSS, and EMX.
  • Extract compact RLCK models for multiport passive components.

What we're looking for

  • Bachelor's degree in Electrical Engineering with 3+ years of RF/Analog circuit design experience and 2+ years of ASIC design experience.
  • Master's degree in Electrical Engineering or a related field with 2+ years of ASIC design, verification, or related work experience.
  • PhD in Electrical Engineering or a related field.
  • 2+ years of academic or professional experience using two or more of the following software: CADENCE, Virtuoso, or ADS.
  • Experience in the design, EM simulation, and circuit modeling of passive RF components for RFIC designs.
  • Experience in the design and simulation of inductors, transformers, MOM capacitors, and passive filters (preferred).
  • Demonstrated abilities with EM simulation techniques and tools including MoM EM solvers, HFSS, and EMX (preferred).
  • Experience with circuit design and layout using Cadence tools and Agilent ADS (preferred).

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