Digital Signal Processing and System Validation Engineer

What you'll do

• Design digital signal processing blocks for next-generation optical data center connectivity products.
• Validate ASIC architecture during both pre-silicon and post-silicon stages.
• Translate CDR and equalization architectures into Verilog code for logic synthesis.
• Implement high-speed DSP algorithms including FFE, DFE, and CDR adaptation for PAM4 signals.
• Perform signal integrity and power integrity modeling for high-speed designs.
• Optimize logic for low power consumption, timing margins, and design-for-test (DFT) requirements.
• Conduct synthesis, clock domain crossing (CDC), and static timing analysis.
• Execute Verilog-HDL/SystemVerilog coding and simulations using tools like Matlab, Simulink, and NCVerilog.

What we're looking for

• MS in Electrical Engineering or Computer Engineering with 10+ years experience, or a PhD with 7+ years of experience.
• Experience in digital signal processing design for SerDes and serial link high-speed data center networking.
• Experience in post silicon validation of digital and analog mixed-signal IPs.
• Deep understanding of ADC and analog based optical and electrical interconnect architectures like PAM4 and NRZ.
• Experience translating CDR and equalization architectures into Verilog code for logic synthesis.
• Proficiency with Matlab, Simulink, and Verilog-HDL/System Verilog coding.
• Experience with front end tools such as NCVerilog, NCSIM, Simvision, and Spyglass.
• Exposure to Design for test (DFT), scan concepts, synthesis, CDC, and static timing analysis.