DFT ATPG Design and Test Engineer

What you'll do

• Own the generation, validation, and delivery of scan test patterns for next-generation CPU cores and caches.
• Partner with product test teams to troubleshoot pattern, model, and netlist issues during test bring-up.
• Improve scan architecture, coverage, test models, and execution methods to enhance overall product quality.
• Perform ATPG pattern and gate-level netlist analysis to resolve testability and coverage issues.
• Collaborate with physical design engineers to support design closure through timing, clock-domain crossing, and power analysis.
• Address DFT requirements for high-frequency CPU designs while minimizing impact on performance.
• Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.

What we're looking for

• A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field is preferred.
• Experience with design-for-test methodologies, specifically scan test and automatic test pattern generation (ATPG).
• Strong working knowledge of industry-standard ATPG tools for pattern generation and fault coverage.
• Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.
• Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory built-in self-test concepts.
• Experience with multi-clock and multi-power-domain designs.
• Familiarity with static timing analysis, clock-domain crossing analysis, static power analysis, and physical design closure.
• Experience in CPU or cache architecture or related ASIC environments is preferred.