Design Verification Engineer

Microsoft

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$85,400–$168,100 / yr
Posted
5 days ago
Freshness
Confirmed live today
Closes
Apr 29, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $205k
This role $127k
$67k $261k
below market most similar roles pay here above market

This role pays less than 99% of similar roles. Most pay $168,500–$241,750 — the blue band above. At the midpoint, this role pays about $127k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 651 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 605 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

The Design Verification Engineer joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on delivering automation and verification needs to scale next-generation Fabric interconnect and Memory Controller technologies for Microsoft’s cloud hardware. The engineer will contribute to the verification of fabric interconnects or memory subsystems by developing UVM and SystemVerilog based verification environments at the integration level. Key responsibilities include applying Formal based methods, running and debugging simulations to drive quality, and innovating to improve verification efficiency through new methodologies or tools. The position requires proficiency in Python, TypeScript, and generative AI solutions. Candidates should possess knowledge of CHI, AMBA, JEDEC, and DFI protocols, as well as experience with memory controllers, coherency, virtualization, security, interrupts, PCIe, CXL, and protocol bridges.

What does a Design Verification Engineer earn?

Median $187850 from 78 postings across 9 companies.

See salary data

What you'll do

  • Contribute to the verification of fabric interconnects or memory subsystems.
  • Develop UVM and System Verilog based verification environments at the integration level.
  • Apply formal-based methods to drive hardware quality.
  • Run and debug simulations to identify and resolve issues.
  • Innovate new methodologies and tools to improve verification efficiency.
  • Apply generative AI solutions to verification workflows and daily tasks.
  • Write IP, block, or subsystem level test plans and develop corresponding tests.
  • Perform coverage signoff and debug failures throughout the product cycle.

What we're looking for

  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field OR equivalent experience.
  • Ability to meet Microsoft, customer, and/or government security screening requirements.
  • Must provide proof of citizenship or U.S. permanent residency for export-controlled information access.
  • Master's Degree in a relevant field OR Bachelor's Degree with 2+ years of technical engineering experience (preferred).
  • 3+ years of related technical engineering experience (preferred).
  • Demonstrated understanding of CHI, AMBA, JEDEC, and DFI protocols (preferred).
  • Demonstrated understanding of memory controllers, fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges (preferred).
  • Proficiency in Python and TypeScript with software development and automation skills (preferred).

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