Design Verification Engineer, Leo Payload FPGA

Amazon Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$176,600–$247,300 / yr
Posted
1 day ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k
This role $212k
$133k $260k
below market most similar roles pay here above market

This role pays more than 68% of similar roles. Most pay $162,000–$214,250 — the blue band above. At the midpoint, this role pays about $212k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 648 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 642 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer, Leo Payload FPGA

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The Design Verification Engineer, Leo Payload FPGA joins the Leo Production team to verify FPGA solutions for a satellite communication system. This role involves creating and maintaining verification environments and test suites for FPGA based subsystems, specifically focusing on digital designs for networking functions. The engineer will define, develop, and implement UVM test environments, develop constrained-random, metric-driven test plans, and create reusable Verification IP. Key responsibilities include analyzing coverage metrics, supporting process upgrades, and mentoring junior engineers. The position requires proficiency in System Verilog, UVM, and scripting languages like Python or Perl. The work involves verifying FPGAs performing signal processing and control functions, as well as participating in the development and deployment of networking and satellite bus FPGAs within a new satellite constellation project.

What does a Design Verification Engineer earn in California?

Median $199500 from 61 postings across 7 companies.

See salary data

Skills

System Verilog UVM FPGA Python Perl Verification IP Coverage Metrics Simulation Networking Digital Design Signal Processing

What you'll do

  • Develop and maintain UVM test environments and test suites for FPGA-based subsystems.
  • Create configurable, self-checking testbenches using System Verilog and UVM.
  • Develop constrained-random, metric-driven test plans for signal processing and control functions.
  • Collect and analyze coverage metrics to improve the effectiveness of test cases.
  • Create reusable Verification IP to be shared across the organization.
  • Support the implementation of process and methodology upgrades.
  • Mentor junior engineers on verification tasks and best practices.
  • Participate in the development and deployment of networking and satellite bus FPGAs.

What we're looking for

  • Must be a U.S. citizen, national, permanent resident, or lawfully admitted as a refugee or granted asylum.
  • Bachelor's degree in Electrical Engineering or a related field.
  • Experience identifying bugs in architecture, algorithms, functionality, and performance with strong debugging skills.
  • Experience verifying logic at multiple levels from IP blocks to SoCs to full system testing.
  • Master's degree in Electrical or Communications Engineering or a related field (preferred).
  • Experience with industry standard tools and scripting languages like Python or Perl for automation (preferred).
  • Export Control Requirement.

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