Design Verification Engineer, DDR Memory Subsystem

Microsoft

Confirmed live 2 days ago Trusted

Quick summary

Work type: On-site
Location: —
Salary: $102,100–$202,200 / yr
Posted: 25 days ago
Freshness: Confirmed live 2 days ago
Closes: Feb 13, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k

This role $152k

$87k most similar roles pay here $240k

This role pays less than 86% of similar roles. Most pay $168,500–$214,000 — the shaded band above. At the midpoint, this role pays about $152k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 598 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 586 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · Design Verification Engineer, DDR Memory Subsystem

Role Posting Log in to save

Design Verification Engineer - DDR Memory Subsystem The Design Verification Engineer - DDR Memory Subsystem joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on the verification of features within the Memory Controller IP or Subsystem to ensure high-quality hardware manufacturing for cloud infrastructure. The engineer will collaborate with partner teams to define verification strategies and test plans while developing UVM-based or Formal verification environments. Day-to-day responsibilities include running and debugging simulations, applying random-stimulus and coverage-based techniques to identify bugs, and utilizing generative AI solutions to improve efficiency. Key technical requirements include proficiency in SystemVerilog, Python, and familiarity with CHI, AMBA protocols, JEDEC specifications, and fabric interconnects. The role addresses the critical challenge of ensuring reliable, high-volume production for advanced computer chips used in large-scale cloud computing environments.

Skills

UVM System Verilog Python Formal Verification PCIe CXL AMBA CHI JEDEC Memory Controller Generative AI Verification Methodology

What you'll do

Own the verification of features within the Memory Controller IP or Subsystem.
Collaborate with partner teams to define verification strategies and test plans.
Develop UVM-based and Formal verification environments to drive product quality.
Run and debug simulations using random-stimulus and coverage-based techniques.
Innovate new methodologies and tools to improve overall verification efficiency.
Integrate generative AI solutions into daily verification workflows.
Coach and mentor team members in specific areas of technical expertise.

What we're looking for

Master's degree plus 1 year of experience, Bachelor's degree plus 2 years of experience, or equivalent experience in engineering.
Ability to pass Microsoft Cloud Background Check and meet export control regulations.
Proof of citizenship, residency, or other protected status is required for export control eligibility.
Doctorate or Master's with 3 years experience, or Bachelor's with 5 years experience (preferred).
Understanding of CHI, AMBA protocols, and JEDEC specifications (preferred).
Knowledge of memory controllers, fabric interconnects, coherency, security, interrupts, PCIe, CXL, and protocol bridges (preferred).
Experience in IP verification from definition to silicon, including test plans, debugging, and coverage signoff (preferred).
Proficiency with UVM, SystemVerilog, formal test benches, Python scripting, and generative AI applications (preferred).

Similar roles

ASIC Design Verification Engineer

Cisco

San Jose, CA 3 days ago $167,700–$245,200

System Verilog UVM ASIC Verification Python Perl C C++ Emulation Formal Verification SoC Architecture Silicon Bring-up Post-Silicon Debug

7+ yrs exp

Save

Design Verification Engineer

Microsoft

8 days ago $102,100–$202,200

UVM System Verilog Python Formal Verification PCIe CXL AMBA CHI Fabric Interconnects Generative AI Simulation Coverage Signoff SVTB

2+ yrs exp Hybrid

Save

Formal Design Verification Engineer

Microsoft

36 days ago $119,800–$234,700

Formal Verification UVM System Verilog Python CHI AMBA PCIe CXL Fabric Interconnects Generative AI SVTB Silicon Engineering Verification Methodology

5+ yrs exp

Save

Senior Fabric Design Verification Engineer

Microsoft

2 days ago $119,800–$234,700

UVM System Verilog Python CHI AMBA PCIe CXL Fabric Interconnects Generative AI Simulation

5+ yrs exp Hybrid

Save

Senior PCIe Bridge Design Verification Engineer

Microsoft

2 days ago $119,800–$234,700

PCIe UVM System Verilog Python CHI AXI Simulation Generative AI Coverage Signoff

5+ yrs exp Hybrid

Save

Design Verification Engineer, Memory Subsystem

Qualcomm

Santa Clara, CA 25 days ago $153,200–$229,800

SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification UPF AXI APB AHB DFI JEDEC DDR LPDDR HBM Constrained-Random Verification Coverage-Driven Verification Simulation Waveform Analysis

4+ yrs exp

Save