Senior PCIe Bridge Design Verification Engineer

Microsoft

Confirmed live yesterday Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Salary
$119,800–$234,700 / yr
Posted
1 day ago
Freshness
Confirmed live yesterday
Closes
Mar 8, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $177k
$106k most similar roles pay here $248k

This role pays less than 52% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 598 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 586 roles with salary data.

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At a glance

TL;DR · Senior PCIe Bridge Design Verification Engineer

The Senior PCIe Bridge Design Verification Engineer joins the Compute Silicon & Manufacturing Engineering team to support the development of high-performance computer chips for cloud infrastructure. In this role, you will own or lead the verification of complex Peripheral Component Interconnect Express (PCIe) Bridge IP flows by collaborating with partner teams to define strategies and test plans. You will build UVM-based verification environments, run simulations, and apply random-stimulus and coverage-based techniques to identify bugs. The position requires expertise in SystemVerilog Test Bench, Python for post-processing, and the application of generative AI solutions to improve verification efficiency. You will work on critical hardware components like Azure Cobalt, focusing on technical challenges involving PCIe, Coherent Hub Interface (CHI), and Advanced eXtensible Interface (AXI) protocols to ensure high-quality silicon production for large-scale cloud environments.

What you'll do

  • Own or lead the verification of complex PCIe Bridge IP flows.
  • Define verification strategies and test plans in collaboration with partner teams.
  • Develop UVM-based verification environments to run and debug simulations for quality assurance.
  • Apply random-stimulus and coverage-based techniques to identify bugs and meet test plan goals.
  • Innovate new methodologies and tools to improve overall verification efficiency.
  • Integrate generative AI solutions into daily verification workflows and tasks.
  • Provide technical leadership by coordinating work across teams and driving verification closure.

What we're looking for

  • A Bachelor's degree plus 5 years of experience, a Master's plus 4 years, or a Doctorate plus 1 year of technical engineering experience is required.
  • Candidates must be able to pass the Microsoft Cloud Background Check and meet export control regulations.
  • Proof of citizenship or protected status is required to access export-controlled information.
  • Preferred candidates should have at least 5 years of pre-silicon subsystem or IP verification experience.
  • Preferred candidates should have at least 3 years of PCIe experience.
  • Experience verifying designs using PCIe, CHI, and AXI protocols or protocol bridges is preferred.
  • Proficiency in UVM, SystemVerilog, and Python for test bench creation and post-processing is preferred.
  • Experience applying generative AI solutions to verification tasks is preferred.

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