Design Verification Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$120,000–$192,000 / yr
Employment
Full-time
Posted
160 days ago
Freshness
Confirmed live yesterday
Closes
Nov 17, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k
This role $156k
$107k $246k
below market most similar roles pay here above market

This role pays less than 85% of similar roles. Most pay $169,625–$230,087 — the blue band above. At the midpoint, this role pays about $156k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 279 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 168 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Design Verification Engineer

Role Posting Log in to save

JOB TITLE: Design Verification Engineer The Design Verification Engineer joins the CSG group to support the development of Tomahawk ASICs for Scale-Out and Scale-Up AI Networks. This role involves verifying cutting-edge network switch routing designs, specifically focusing on L2/L3 Network Switching and various subsystems. Daily responsibilities include creating in-depth test plans for traffic streaming, management, scheduling, and shaping, as well as latency and performance characterization. The engineer will develop verification environments, testbenches, and APIs, while implementing test plans into executable suites. Required technical skills include proficiency in Systemverilog, Verilog, UVM, Perl, Python, and Object Oriented Programming. The work addresses the technical challenge of managing extremely large volumes of traffic reaching several hundreds of Terabits/sec across various line interfaces and protocols.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

SystemVerilog UVM Verilog Python Perl ASIC SOC Routing OOP Makefiles Code Coverage Hardware Description Languages Digital Design

What you'll do

  • Verify L2/L3 network switching and routing ASICs and their internal subsystems.
  • Create in-depth test plans for traffic streaming, management, scheduling, and performance characterization.
  • Develop verification environments including testbenches, APIs, scripts, and Makefiles.
  • Implement test plans into executable suites using a SystemVerilog verification environment.
  • Execute the verification process to completion using functional and code coverage metrics.
  • Manage the end-to-end verification process from test plan definition to coverage closure.

What we're looking for

  • Must have an MSEE or BSEE with a concentration in digital design and excellent academic standing.
  • Must have 8+ years of experience with a BS degree, 6+ years with an MS degree, or 3+ years with a PhD.
  • Must be familiar with hardware description languages including Verilog, SystemVerilog, and UVM.
  • Must be familiar with scripting languages such as Perl and Python and Object Oriented Programming.
  • Must have exposure to cutting-edge verification and validation techniques using Object Oriented modular reusable environments.
  • Must have strong experience in the end-to-end verification process from test plan definition to coverage closure on mass production ASIC/SOC silicon.
  • Must possess excellent verbal and written communication skills.

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