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About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
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3499 open roles
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Listed pay typically runs
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As a Design Verification Engineer, you will join a hardware team to ensure bug-free first silicon for SoC and IP designs. You will manage all phases of pre-silicon verification, including establishing DV methodologies, developing test plans based on micro-architecture, and building scalable, portable verification environments. Your daily work involves creating stimulus, checkers, assertions, and trackers while performing design bring-up, regression enabling, and debugging test failures. You will use SystemVerilog and UVM to stress designs and utilize LLMs to improve execution efficiency and quality. Key technical requirements include proficiency with simulators, waveform viewers, build automation, coverage collection, and gate-level simulations. You may also apply knowledge of UPF, formal verification, and scripting languages like Python, Perl, or TCL to solve complex hardware verification problems.
What does a Design Verification Engineer earn?
Median $191200 from 85 postings across 10 companies.
Create comprehensive test plans based on design specifications and micro-architecture.
Develop scalable and portable verification environments using SystemVerilog and UVM.
Build verification components including stimulus, checkers, assertions, and trackers.
Execute verification plans for design bring-up and regression enabling.
Debug test failures and fix bugs to ensure bug-free first silicon.
Track and report verification progress using bugs and coverage metrics.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Perform sign-off for RTL freeze and tape-out.
What we're looking for
BS degree in a technical subject area and a minimum of 3 years of relevant industry experience.
MS degree in a technical subject area and relevant industry experience (preferred).
Strong knowledge of OOP, SystemVerilog, and UVM (preferred).
Strong knowledge in developing scalable and portable testbenches (preferred).
Proven experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, and gate-level simulations (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Knowledge of scripting languages such as Python, Perl, or TCL (preferred).