below marketmost similar roles pay hereabove market
This role pays more than
66%
of similar roles. Most pay
$169,625–$235,250
— the blue band above.
At the midpoint, this role pays about
$214k
versus about
$202k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3499 open roles
on FindRole.
Listed pay typically runs
$166,600–$277,600
across 2707 roles with salary data.
JOB TITLE: Design Verification Engineer
The Design Verification Engineer joins a hardware group to ensure bug-free first silicon for SoC and IP designs. This role involves managing all phases of pre-silicon verification, including establishing methodologies, developing test plans, and building verification environments with stimulus, checkers, assertions, and trackers. The engineer will execute verification plans, perform design bring-up, manage regressions, and debug test failures to achieve sign-off for RTL freeze and tape-out. Key technical requirements include proficiency in SystemVerilog, UVM, and Object-Oriented Programming to create scalable, portable testbenches. Candidates must use simulators, waveform viewers, and coverage collection tools, while utilizing LLMs for efficient execution. Additional skills include scripting in Python, Perl, or TCL, and knowledge of power-aware UPF methodologies, formal verification, and serial or parallel protocols like PCIe, USB, or DDR.
What does a Design Verification Engineer earn in California?
Median $195350 from 60 postings across 7 companies.
Create detailed test and coverage plans based on the micro-architecture and design specifications.
Develop scalable and portable verification methodologies and environments using SystemVerilog and UVM.
Build verification components including stimulus, checkers, assertions, trackers, and coverage.
Execute verification plans for design bring-up and regression enabling.
Debug test failures and fix bugs identified during regression cycles.
Track and report verification progress using metrics such as bug counts and coverage.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Perform pre-silicon verification to ensure bug-free first silicon for SoC and IP designs.
What we're looking for
BS degree in a technical subject area and a minimum of 3 years of relevant industry experience.
MS degree in a technical subject area and relevant industry experience (preferred).
Strong knowledge of OOP, SystemVerilog, and UVM (preferred).
Strong knowledge in developing scalable and portable testbenches (preferred).
Proven experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, and gate-level simulations (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Knowledge of scripting languages such as Python, Perl, or TCL (preferred).