Design Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Seattle, WA
Salary: $142,300–$263,300 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k

This role $203k

$128k $278k

below market most similar roles pay here above market

This role pays more than 56% of similar roles. Most pay $168,500–$230,087 — the blue band above. At the midpoint, this role pays about $203k versus about $199k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the Hardware Technology team to verify the functionality and performance of premier SOCs. This role involves owning the quality of the SOC, IP, or subsystems by reviewing design and architecture specifications and collaborating with design and micro-architecture teams. Key responsibilities include developing test plans, coverage plans, and next-generation verification methodologies and testbenches. The engineer must understand functional and performance goals to test optimally while communicating with software teams to identify use cases and corner conditions. Required skills include SystemVerilog, digital simulation, debug, and knowledge of computer architecture and digital design fundamentals. Candidates should also possess software programming skills in Python or Perl, and experience with UVM, constrained random verification, functional coverage, and assertion methodology. Work involves subsystems like Neural Engines, DRAM, and high-speed IO.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

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Skills

SystemVerilog UVM Python Perl C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture Data Structures Algorithms PCI Express DisplayPort MIPI VP9 AV1

What you'll do

Verify the functionality and performance of Apple’s premier SOCs, IPs, or subsystems.
Review design and architecture specifications to ensure quality and performance goals are met.
Develop comprehensive test plans, test cases, and coverage plans for hardware designs.
Define next-generation verification methodologies and build complex testbenches.
Communicate with design, architecture, and software teams to identify use cases and corner conditions.
Execute digital verification processes including constrained random verification and functional coverage.
Utilize SystemVerilog, UVM, and scripting languages like Python or Perl to perform simulations and debugging.

What we're looking for

Minimum of a BS degree.
Minimum of 3 years of relevant industry experience.
Skilled in digital verification including constrained random verification, functional coverage, code coverage, and assertion methodology (preferred).
Knowledge of SystemVerilog, digital simulation, and debug (preferred).
Knowledge of computer architecture and digital design fundamentals (preferred).
SW programming skills with knowledge of data structures and algorithms (preferred).
Experience with Python, Perl, or similar scripting languages (preferred).
Knowledge of verification methodologies like UVM (preferred).