Design for Test Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $146,717–$218,000 / yr
Posted: 53 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $155k

This role $182k

$113k $229k

below market most similar roles pay here above market

This role pays more than 74% of similar roles. Most pay $123,881–$185,673 — the blue band above. At the midpoint, this role pays about $182k versus about $155k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Design for Test Engineer

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The Design for Test Engineer will join the hardware team to develop and implement DFT architecture and specifications. The role involves coding Verilog Register Transfer Language for DFT logic and collaborating with designers to integrate implementations while addressing static timing analysis, physical, power, and logical issues. Key responsibilities include coordinating with design verification teams to verify RTL and gate-level implementations, reviewing coverage, and implementing engineering change orders. The engineer will generate ATPG structural test vectors, analyze test coverage, and debug test vectors on silicon. Required skills include proficiency in Verilog, MBIST, march algorithms, JTAG architecture, and Python or Perl scripting. The position also requires using VCS or NCSIM for simulations and performing silicon failure diagnosis from automated test equipment to improve manufacturing yields.

Skills

Verilog RTL DFT ATPG STA MBIST JTAG Python Perl VCS NCSIM Gate-level Simulation Silicon Diagnosis ATE Low-power Design ECOs

What you'll do

Develop and implement DFT architecture and document technical specifications.
Code Verilog RTL for DFT logic and implement necessary infrastructure.
Partner with designers to resolve STA, physical, power, and logical issues.
Coordinate with DV teams to verify DFT implementations and implement ECOs.
Generate ATPG structural test vectors and analyze test coverage.
Debug and bring up test vectors on silicon with test engineers.
Support test time reduction and silicon diagnosis efforts.
Automate DFT design flows using Python or Perl scripting languages.

What we're looking for

Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
2 years of experience in the job offered or a related occupation.
Experience designing and verifying RTL using Verilog hardware description language.
Knowledge of MBIST, march algorithms, and memory fault models.
Experience designing JTAG architecture and programming DFT control registers for chip testing.
Ability to automate DFT design flows using Python or Perl scripting languages.
Knowledge of STA for timing analysis.
Experience running RTL and gate-level simulations using industry-standard tools like VCS or NCSIM.