Design for Test Engineer

What you'll do

• Perform scan insertion and Automatic Pattern Generation (ATPG) during the DFT design development phase.
• Deliver configurations and scripts to the Front-end team for use during RTL generation.
• Debug and provide support to the Front-end team to ensure high-quality scan insertion during synthesis.
• Maintain and improve ATPG flows to achieve high stuck-at coverage using ATPG tools.
• Debug simulation and silicon failures by implementing RTL, script, or configuration changes.
• Generate partition-level and top-level patterns to meet targeted coverage project specifications.
• Create infrastructure to improve the design cycle and implement checks to catch RTL issues early.
• Implement DFT infrastructure and work with the DV team to verify implementations and execute ECOs.

What we're looking for

• Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
• 2 years of experience in the job offered or a related occupation.
• Experience using Verilog to write RTL for DFT IP.
• Experience using RTL Design for DFT features such as scan codec, ATPG isolation, and scan routing.
• Experience using scripting languages like Python, Perl, or TCL for automation of design flows, verification, synthesis, and modeling.
• Experience using basic FE tools (CDC, RDC, Lint) with an understanding of clock and reset domains.
• Experience using synthesis tools to set up constraints and configurations.
• Experience using ATPG tools for Scan DRC and ATPG coverage analysis and improvement.