Design for Test Engineer

What you'll do

• Manage all aspects of design development for large SoC blocks including internal and external IP integration.
• Design system bus and control bus logic to connect IP blocks to the main SoC infrastructure.
• Own the Integration Specification for assigned design projects.
• Integrate and optimize memories and hard macros required for specific blocks.
• Execute synthesis, netlist generation, and timing closure for the block.
• Develop and maintain methodologies, flows, and checks for the design process.
• Implement UPF flows for power islands and voltage islands to manage low-power applications.
• Ensure high-quality delivery by incorporating proper checks at every stage of the design process.

What we're looking for

• BSEE/MSEE, MSCE, or PhD program.
• Knowledge of ASIC design flow, FE and Design verification, synthesis, scripting, and netlist generation (preferred).
• Proven track record of high performance designs for low power applications, RTL design, and timing closure on large complex designs (preferred).
• SOC IP integration and RTL Design for performance, low area, and low power (preferred).
• FE synthesis with DFT insertion (preferred).
• ASIC design flow and netlist flow checks including CDC and Logical Equivalence (preferred).
• UPF flow for power islands as well as voltage islands (preferred).
• Familiarity with DFT and backend related methodology and tools (preferred).