Design for Test Engineer

What you'll do

• Own all aspects of development design for large SOC blocks including internal and external IP integration.
• Design system bus and control bus logic for connecting IP blocks to the main SOC infrastructure.
• Manage the Integration Spec for the design project.
• Integrate and optimize memories and hard macros required for the block.
• Perform synthesis, netlist generation, and timing closure for the assigned block.
• Develop and maintain methodology, flows, and checks for your specific designs.
• Implement proper checks at every stage of the process to ensure high quality and timely delivery.

What we're looking for

• Must be enrolled in a BSEE, MSEE, MSCE, or PhD program.
• Knowledge of ASIC design flow, FE, Design verification, synthesis, scripting, and netlist generation (preferred).
• Proven track record of high performance designs for low power applications, RTL design, and timing closure on large complex designs (preferred).
• Experience with SOC IP integration and RTL Design for performance, low area, and low power (preferred).
• Experience with FE synthesis with DFT insertion (preferred).
• Knowledge of ASIC design flow and netlist flow checks such as CDC and Logical Equivalence (preferred).
• Experience with UPF flow for power islands and voltage islands (preferred).
• Familiarity with DFT and backend related methodology and tools (preferred).