STA Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Fort Collins, CO
Employment: Full-time
Posted: 96 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $166k

$120k $213k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $128,750–$204,012.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · STA Engineer

Role Posting Log in to save

STA Engineer The STA Engineer joins the ASIC Products Division to support the design and manufacture of next-generation, high-performance, and power-efficient ASICs. This role involves managing all aspects of timing closure, including debugging constraints, facilitating logic changes, and constructing timing flows. The engineer will collaborate with Physical Design and Logic Design teams to identify issues, create timing ECOs for project tapeouts, and implement timing infrastructure. Key responsibilities include deep analysis of timing paths, maintaining scripts, and documenting guidelines. Candidates must possess an MSEE and over ten years of relevant industry experience. Required skills include proficiency in Perl and TCL, familiarity with SPICE models, and expertise in sub-micron technologies. The role requires deep knowledge of noise, cross-talk, OCV effects, and Multi-Scenario Timing Closure for large, complex SoC designs.

Skills

STA Perl TCL SPICE SoC Design ECO Multi-Scenario Timing Closure OCV Cross-talk Circuit Modeling Synthesis Physical Design Logic Design Timing Closure

What you'll do

Perform all aspects of timing closure for high-performance, power-efficient ASICs.
Debug constraints and facilitate logic changes with design teams to improve timing.
Create and implement timing ECOs for project tapeouts.
Develop and maintain scripts and methodologies for analysis and automated runs.
Conduct deep analysis of timing paths to identify and resolve critical issues.
Implement and manage timing infrastructure for the design process.
Document technical guidelines and specifications for timing analysis.

What we're looking for

MSEE or equivalent degree is required.
10+ years of relevant industry experience is required.
5-10 years of hands-on experience in STA is required.
Familiarity with timing of large high-performance SoC designs in sub-micron technologies is required.
Proficiency in STA standards, timing closure, noise, cross-talk, and OCV effects is required.
Strong programming skills with Perl and TCL are required.
Proficiency in timing flows using industry standard tools is required.
Experience with Multi-Scenario Timing Closure and familiarity with ECO techniques are highly beneficial (preferred).

Similar roles

Design Engineer, STA

Broadcom

Fort Collins, CO 56 days ago $109,700–$175,500

Static Timing Analysis (STA) Synopsys PrimeTime Cadence Tempus Tcl Python Perl Ruby Linux VLSI Design ASIC Physical Design MMMC POCV SOCV LVF PBA SPICE Signal Integrity Clock Network Design

8+ yrs exp

Save

Design Engineer, STA

Broadcom

Fort Collins, CO 64 days ago $129,400–$207,000

VLSI ASIC Physical Design Static Timing Analysis Synopsys PrimeTime Cadence Tempus TCL Python Ruby BASH SPICE CMOS Clock Networks Signal Integrity Crosstalk POCV SOCV LVF PBA 3DIC

10+ yrs exp

Save