CPU CDC/STA Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $150,400–$277,600 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $203k

This role $214k

$135k $293k

below market most similar roles pay here above market

This role pays more than 59% of similar roles. Most pay $172,963–$233,050 — the blue band above. At the midpoint, this role pays about $214k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · CPU CDC/STA Engineer

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The CPU CDC/STA Engineer will join the hardware team to analyze designs and drive fixes while developing, maintaining, and improving Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and Static Timing Analysis (STA) constraints and methodologies for CPUs across multiple design sites. The engineer is responsible for developing CDC and RDC sign-offs, enhancing key STA checks, and recommending SystemVerilog assertions to support constraints. Daily tasks include debugging vendor tool problems, collaborating with EDA vendor representatives, and working closely with RTL, Verification, CAD, and Physical Design teams. Required skills include scripting with TCL or Perl and experience in STA, CDC, or RDC solutions. Preferred qualifications include experience with SystemVerilog Assertions, Design Verification simulations, Verilog, and tools such as Spyglass, VC-Static, PrimeTime, or Meridian.

Skills

Static Timing Analysis (STA) Clock Domain Crossing (CDC) Reset Domain Crossing (RDC) SystemVerilog Assertions (SVA) TCL Perl Verilog Spyglass VC-Static PrimeTime Meridian Design Verification Lint RTL

What you'll do

Develop, improve, and maintain CDC and RDC sign-offs for CPU designs.
Maintain and improve STA constraints and methodologies across multiple design sites.
Recommend SystemVerilog assertions to support CDC, RDC, and STA constraints.
Develop and enhance key STA checks and associated sign-offs for CPUs.
Debug vendor tool problems and provide solutions to design teams.
Work with EDA vendor representatives to drive new methodologies and tool improvements.

What we're looking for

Minimum BS degree and 3+ years of relevant industry experience.
Scripting experience with TCL or Perl.
Experience in one or more of the following: Static Timing Analysis (STA), Clock-Domain Crossing (CDC), or Reset Domain Crossing (RDC) solutions.
Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations (preferred).
Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian (preferred).
Experience in Verilog (preferred).