CPU CDC/RDC/STA Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 40 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $203k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

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At a glance

TL;DR · CPU CDC/RDC/STA Engineer

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The CPU CDC/RDC/STA Engineer will join the hardware team to analyze designs and drive fixes while developing, maintaining, and improving Lint, Clock Domain Crossing, Reset Domain Crossing, and Static Timing Analysis constraints and methodology for CPUs across multiple design sites. The role involves developing CDC and RDC sign-offs, recommending SystemVerilog assertions to RTL and DV teams, and highlighting structural issues to designers. Key responsibilities include maintaining STA checks, debugging vendor tool problems, and collaborating with EDA representatives to drive new methodologies. Candidates must possess experience with Clock-Domain Crossing, Reset Domain Crossing, Verilog, and scripting in TCL or Perl. Proficiency with Synopsys or Real Intent tools is required, while knowledge of Spyglass, VC-Static, PrimeTime, or Meridian is preferred for this CPU design and verification work.

Skills

CDC RDC STA SystemVerilog Assertions Verilog TCL Perl Synopsys Real Intent Spyglass VC-Static PrimeTime Meridian RTL Design Design Verification

What you'll do

Develop, improve, and maintain CDC and RDC sign-offs for CPU designs.
Create and maintain STA constraints and associated sign-off methodologies for CPUs.
Recommend SystemVerilog assertions to support CDC, RDC, and STA constraints and assumptions.
Identify CDC/RDC issues in RTL and provide structural solutions and education to the RTL team.
Debug vendor tool problems and collaborate with designers to resolve technical issues.
Work with EDA vendor representatives to drive tool improvements and new methodologies.
Maintain and improve Lint, CDC, RDC, and STA methodologies across multiple design sites.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Experience with Clock-Domain Crossing (CDC) and Reset Domain Crossing (RDC).
Experience with at least one of the following: Synopsys or Real Intent tool.
Scripting experience in TCL or Perl.
Experience in Verilog.
Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations (preferred).
Experience in multi-clock-domain RTL design (preferred).
Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian (preferred).